Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[CakeMonster]

There's two reasons to believe Raptor Lake's performance increase over Alder Lake will be less than Z4 over Z3. Its on the same process as Alder Lake, and Intel's basically already said the design is iterative.

If Z4 has few innovations besides L2, AVX512, PCIE5 and DDR5, then it might actually somewhat disappoint at around ~15% real world performance as those eat some of the transistor bonus that 5nm gives us. I'm certainly not going to believe that just off one out of context slide though.

 

[exquisitechar]

A question concerning that "slide" with the >15% single thread info?

It appears to be a Videocardz created slide. Can it be, well, wrong, as in so many "leaks" lately? Or should I say "outdated".

It isn’t Videocardz created, they almost certainly got their hands on slides, as usual before events like this.

 

[xilli_fiberbit]

Interesting article on X670 and B650 chipset configuration, with block diagram : https://angstronomics.substack.com/p/site-launch-exclusive-all-the-juicy?s=r

The dual X670 chipset : one is connected on CPU and the second one to the first X670, it avoid use of retimers

From CPU :

• One USB 3.2 Gen 2 10Gbps port with BIOS flash capability
• One USB 2.0 port with SecureBIO support for Windows Hello capability

 

[tomatosummit]

They are sandbagging, and so is Intel with Raptorlake.

Remember the Alderlake slide? "Up to 19% single thread performance"?

Yes and I also remember upto 18% ipc improvement for rocketlake that came out as 8-13% .
But I think the alder lake one was for mobile products, not the overclocked desktop stuff.

Anyway "over 15%" is a very bold and suspicious claim.
Read as is it could be that 99% of software sees at least a 15% performance increase but I think it could actually be a statement for the whole product line. The entire range, 5600 - 7600 through to 16 core stuff all seeing at least 15% average performance increases.

I'm very upset at this dashing of my 24core hopes and will take this as a personal slight of amd againt me.

 

[jpiniero]

I'm very upset at this dashing of my 24core hopes and will take this as a personal slight of amd againt me.

There's always Bergamo.

 

[mikk]

Yes and I also remember upto 18% ipc improvement for rocketlake that came out as 8-13% .
But I think the alder lake one was for mobile products, not the overclocked desktop stuff.

18% was accurate over Skylake.

Intel Core i9-11900K & i5-11600K „Rocket Lake-S“ im Test

Intels finale 14-nm-CPUs für Desktop-PCs alias Rocket Lake-S setzen im Test auf die Brechstange, um auch gegen den Vorgänger zu bestehen.

www.computerbase.de

They are sandbagging, and so is Intel with Raptorlake.

Remember the Alderlake slide? "Up to 19% single thread performance"?

Actually they might troll us, we will see. The footnote from this slide might tell us more tomorrow.

 

[Panino Manino]

Which emulator? I

CPU 2021 Benchmarks - Compare Products on AnandTech has a dolphin test. The 5950x is about 15% behind the 12900k. For other emulators, Zen 4 has a number of changes that will help with emulation, such as the increase in L2 and some floating-point improvements. Also, unless the emulator is open source, there is no way to know if it is an issue with the way the emulator is written (optimizations for Intel, for example) vs. an actual issue with the chip. I'm a developer by trade, have written (older) emulators (also I've contributed to certain open-source operating systems and drivers), and I can tell you that certain design decisions can absolutely make or break performance on a given architecture.

Dolphin is irrelevant, any low end CPU is enough.
Think something like RPCS3 or Xenia, demanding emulators.

 

[DisEnchantment]

Ahaha, if this is true, which I believe it is, take out the frequency gains, and you're left with low single digit IPC.
Two years, tons of extra Xtors, new high frequency DDR5 but this is all they managed?
Make Skylake refreshes look great in comparison.
Add the cherry on top if this performance "gain" is at 170W TDP.

 

[CakeMonster]

Add the cherry on top if this performance "gain" is at 170W TDP.

170W is likely the spec for AM5, so that mobo's can be built for that headroom in case they need to go that high in the future.

 

[exquisitechar]

Ahaha, if this is true, which I believe it is, take out the frequency gains, and you're left with low single digit IPC.
Two years, tons of extra Xtors, new high frequency DDR5 but this is all they managed?
Make Skylake refreshes look great in comparison.
Add the cherry on top if this performance "gain" is at 170W TDP.

Fully agreed, I can’t believe some of the damage control I’m seeing in other communities. People are pretending that expecting a double digit IPC increase was too much. AMD might fall behind their competitor’s last generation (around launch time) CPU...

 

[maddie]

Ahaha, if this is true, which I believe it is, take out the frequency gains, and you're left with low single digit IPC.
Two years, tons of extra Xtors, new high frequency DDR5 but this is all they managed?
Make Skylake refreshes look great in comparison.
Add the cherry on top if this performance "gain" is at 170W TDP.

Why do you believe it to be true? Any special insight?

 

[DisEnchantment]

Why do you believe it to be true? Any special insight?

These press decks usually get leaked once they are distributed before the event. It happens every time.
I don't think AMD would be sandbagging that much if they are behind. They can get quite loud in their marketing department.

 

[Karnak]

And what if AMD's ST improvement claim is not against Zen3 but rather... a CPU gen from their competition?

Without knowing the footnotes and to what the "1" is referring to it's pointless to draw a conclusion. Just wait a few more hours when we get all the slides which videocardz obviously doesn't have.

 

[NostaSeronx]

Wait, no V-cache by default?

Zen4 with V-Cache is end of era.

Zen3 w/ V-cache => Last Zen3 CPU before Zen4
Zen4 w/ V-cache => Last Zen4 CPU before Zen5

If anyone sees V-cache it means the next-generation is around the corner.

For example, 4th Gen EPYC with V-Cache hasn't been officially announced with a codename yet.

 

[maddie]

These press decks usually get leaked once they are distributed before the event. It happens every time.
I don't think AMD would be sandbagging that much if they are behind. They can get quite loud in their marketing department.

Oh. I thought you might have an idea why the IPC gains appears to be so low even with all the new transistors available.

 

[DisEnchantment]

Oh. I thought you might have an idea why the IPC gains appears to be so low even with all the new transistors available.

No idea why, I have many paid subscriptions but seems nobody had a clue. Everybody seems off just as much as Redgamingtech.
15 % ST perf uplift is baffling indeed though considering the 1.25x advertised process perf uplift and 2x density uplift.

 

[tomatosummit]

I think you guys need to realise what "> more than greater than at least" would imply in this situation.

 

[Saylick]

I think you guys need to realise what "> more than greater than at least" would imply in this situation.

Yeah, maybe there's another slide where they show like 30 benchmarks or use cases, sorted from lowest ST increase to highest, and 15% is on the low end of the plot with the high end being over 30%.

 

[eek2121]

Ahaha, if this is true, which I believe it is, take out the frequency gains, and you're left with low single digit IPC.
Two years, tons of extra Xtors, new high frequency DDR5 but this is all they managed?
Make Skylake refreshes look great in comparison.
Add the cherry on top if this performance "gain" is at 170W TDP.

Even with 170w TDP, Skylake still does not look great, "in comparison". 🤣😂

170W is likely the spec for AM5, so that mobo's can be built for that headroom in case they need to go that high in the future.

No, we are seeing a 170W TDP chip launch with the rest, and it will be a monster, and it will still consume less power than Intel.

These press decks usually get leaked once they are distributed before the event. It happens every time.
I don't think AMD would be sandbagging that much if they are behind. They can get quite loud in their marketing department.

Normally, all the leaked slides come out around now. Yet we've only seen two partial slides. I actually agree with you in principle. My only conclusion is that the press wasn't provided a slide deck in advance.

No idea why, I have many paid subscriptions but seems nobody had a clue. Everybody seems off just as much as Redgamingtech.
15 % ST perf uplift is baffling indeed though considering the 1.25x advertised process perf uplift and 2x density uplift.

If you are giving money to folks like RGT you deserve what you get, no offense. "You get what you pay for".

My advice is free. I say this now, I've said this before, and I'll say this after: if you are paying for 'rumors' or 'leaks', you are literally burning money. It's all on Twitter, Telegram, and elsewhere for free. Folks like RGT and certain folks starting with an "A" grab "info" off these "sources", don't name the actual source, and try to get stuff right. They then try to profit from said venture. They end up being 90% wrong, yet 10% right (the source is usually right, hence the 10%)

Most of the real stuff comes from Telegram, Twitter, etc.

Not that I have an issue with burning money on some stuff, however at least I know I'm literally burning money...

 

[deasd]

No idea why, I have many paid subscriptions but seems nobody had a clue. Everybody seems off just as much as Redgamingtech.
15 % ST perf uplift is baffling indeed though considering the 1.25x advertised process perf uplift and 2x density uplift.

As reference, IIRC Apple switching from A13(7nm) to A14(5nm) result in ~20% perf uplift in both ST and MT with same TDP.
So thats why calling this strange. Maybe just for fun for some guys are start hesitated betting whether Zen4 has IPC regression......

 

[tamz_msc]

6nm I/O die with iGPU - there goes the Rembrandt supply.

 

[DrMrLordX]

That slide is kinda vague. It lines up with the 15-24% IPC increase, depending on how you look at it. At the same time, if you look at it a different way, it doesn't . . .

 

[RnR_au]

15 % ST perf uplift is baffling indeed though considering the 1.25x advertised process perf uplift and 2x density uplift.

Could they be sandbagging due to Zen 5 being on N4(p?) rather than N3?

 

[Tuna-Fish]

I think the big thing is AVX512. When not using that, the uplift will be fairly small, maybe that 15%.

When using AVX512, the uplift will be much more substantial.

 

[gdansk]

In the presentation it sounds like 1T uplift is ">15%" including the clock speed increase.
Well that's less than expected.