Solved! Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Joe NYC]

The 6 nm IO die and updated interfaces could reduce power usage significantly, so I think a chiplet based mobile part will actually do quite well. It is just one link compared to the massive number on Epyc IO die. I assume that a major goal of the new Genoa IO die was to reduce power consumption. The really low power design will be a stacked solution, but that comes later. They will still probably use monolithic die and stacked solutions for lower power parts. Different types of stacking has been used in mobile for a while. Some of the new chip stacking tech can get close to a monolithic die for power consumption, so all mobile parts will probably be in a stacked package of some kind going forward. It would be great if we can get something like a 16 core processor (possibly Zen 4c based cores), a reasonable GPU, and a stack of HBM2E cache. A single stack is 16 GB now. If you had some LPDDR5 or even a ridiculously fast SSD to back it up, then that is plenty.

It could be 1 or 2 links for mobile part. In case of APU, it might be advantageous to have graphics chips separate, just to keep the complexity down, for improved time to market and improved modularity.

If the rumors of small iGPU in IO die are true, low end laptops could use just that, IOD + CCD and higher end APUs could add a dedicated GPU chiplet

BTW, it would be nice to know the cost of the EFB bridge that AMD is using in Mi200. The old problem of HBM was that it almost necessitated using interposer, which added significant cost.

With EFB, without interposer, I wonder how the costs compare.

The cost comparison would be between memory connection inside MCM vs. motherboard connection. Something tells me that it should end up being cheaper to make the connection to memory in MCM than on motherboard...

I think one of the reasons AMD and Intel have not done it is that if you take x amount of memory, for say $200, assuming the costs are equal, you would have:

- mcm + $200
- mobo - $200

Now, let's say CPU MCM is $250, and we may find out why AMD / Intel are reluctant to implement it.

Say the MCM has 50& margin originally.

Next, you add $200 of memory at low to no margin. If Intel AMD sell the new part for $450, Suddenly the gross margin drops from 50% to 27%.

27% Gross margin would give a$$hole Wall Street analysts (like Stacey Rasgon, as example of the worst) green light to shred the company to pieces. It worked against Intel. Intel shredded division after division after it could not make 50% margin. I wonder about the AMD management, if they would let themselves be intimidated the same way, now when AMD is profitable.

 

[Joe NYC]

Zen3d/3+ seems more of a hedge against limited N5(x) capacity than anything else.

Yes, totally. AMD already has a sizeable (and growing) capacity of N7 secured from TSMC. Using it fully is the only way AMD can maintain its current growth rate.

BTW, this is the reason for my rants in another forum. AMD missed the opportunity to show this product (Zen3D) in the best light, which would increase the longevity of these CPUs on the selves, and also, increase lifetime of AM4 socket motherboards by another 1-2 years.

While Zen 4 may be much more attractive, a full system upgrade could end up 2x to 3x the cost of a simple CPU upgrade to higher end Zen 3d for AMD owners.

 

[jamescox]

Yes, totally. AMD already has a sizeable (and growing) capacity of N7 secured from TSMC. Using it fully is the only way AMD can maintain its current growth rate.

BTW, this is the reason for my rants in another forum. AMD missed the opportunity to show this product (Zen3D) in the best light, which would increase the longevity of these CPUs on the selves, and also, increase lifetime of AM4 socket motherboards by another 1-2 years.

While Zen 4 may be much more attractive, a full system upgrade could end up 2x to 3x the cost of a simple CPU upgrade to higher end Zen 3d for AMD owners.

AM4 will be around for a while yet. There has been talk of 8 to 9 month delays with DDR5 due to shortages of the power management chips. With all of the delays, I would guess that anything using DDR5 might be a year away from any serious ramp. Genoa is supposed to be coming in 2022, but it may actually be held back by memory availability.

I don’t think it is much of an issue that AMD didn’t release the v-cache parts. In fact, I think it is better that they didn’t. Intel takes the lead in some things, but it isn’t a clear victory due to the power consumption. Rushing out to release the v-cache would make it look like intel’s part is more competitive than it actually is. There are a bunch of people saying AMD must respond, but I would say that it actually looks better if they don’t. AMD is going to be selling everything they can make for a while yet regardless. I haven’t been following Intel parts since I will almost certainly be buying AMD, but I don’t think Intel will really have a response to the v-cache parts and I think they will likely take the lead in most things, and for certain applications, the lead could be very large. Some applications will get a massive speed-up with that large of cache.

 

[DrMrLordX]

AMD launching Zen3D in November 2021 or January 2022 doesn't really make much difference. Not that this is the Zen3D thread or anything, ya know.

When they launch AM5 + Raphael is going to be a much bigger deal.

 

[eek2121]

Zen3d/3+ seems more of a hedge against limited N5(x) capacity than anything else. It allows them to produce more processors with competitive performance on a node that's no longer leading edge. AMD's biggest issue right now is, oddly, an enviable one, they can't build enough parts to keep the market satisfied. They are literally leveraging 5 different nodes right now: GF12/14 (Dali, etc), N7, N6, preproduction on N5, and, likely, GF12+ for Monet, while also looking at various Samsung nodes. Not making Zen3d would be deliberately avoiding an opportunity to produce products for profit and to support their partners in the rest of the industry by making products that create demand for theirs as well. Intel is going to be supply constrained themselves across their entire lineup with the noted yield issues on 10+, limited capacity for 10sf for TL, limited capacity for 10esf for AL, 14 running flat out to meet OEM volume, etc. It stands to reason that AMD should shovel everything that they can into the market while they can to keep revenues up, to allow more money for R&D and build better relationships with their suppliers. Also, as you gain critical mass in the market, you also coax software makers to begin to optimize more for your products, making your job easier in R&D.

That is why I suspect a much more limited release with Zen 4 than with Zen 3. I could be wrong, but their absolute best option is to keep most of the volume on N7 or N6 until Apple’s volume sales leave N5. They can do this by initially restricting Zen 4 to low volume, high margin parts.

How it looks today:

N7 - Milan, Milan-X, Vermeer, Zen3D (also Zen 2 parts), RDNA, RDNA2, etc.

What the future could look like:
N7 - Milan, Milan-X, Vermeer, Zen3D
N6 - Rembrandt, Navi33/34
N5 - Genoa, Navi31, Raphael, Navi31/32

 

[jamescox]

AMD launching Zen3D in November 2021 or January 2022 doesn't really make much difference. Not that this is the Zen3D thread or anything, ya know.

When they launch AM5 + Raphael is going to be a much bigger deal.

This isn’t the v-cache thread, but what is going on with the v-cache parts might be relevant to Zen 4 in many ways. With the shortages, it will be difficult to launch a DDR5 only platform. With the separate IO die, AMD has the possibility of mixing different generation parts if they are still serdes based IFOP, which Zen 4 seems to be. Stacked connections for chiplets doesn’t seem to be happening until zen 4c. Zen 5 may also still have a serdes based IFOP variant in addition to a stacked variant.

I can’t keep track of all of the code names floating around, so I may be missing things, but I have wondered if a zen 4 chiplet might get paired with an older IO die if the DDR5 ramp turns out to be a disaster. AMD has a lot of options with the level of modularity in their architecture. I suspect that the v-cache parts may have been intended for server only, but the cost made them reasonable for higher end desktop parts. The Zen X3D parts are already extending AM4 for about 2 extra years. With the extremely large cache, DDR5 bandwidth will be less important anyway. I don’t know if it is clear yet wether Zen X3D is just the original Zen 3 die or if it has some other updates. I am thinking that Zen 3+ is a different die, but I haven’t had time to look up much about it. They seem like they would have been parallel projects, so we might see 2 different products extending AM4.

Also, to get an idea of what is going on at AMD, you have to look at all of their parts. There is a lot of shared IP and possibly shared die going forward. We still don’t know if the rumored 512 MB infinity cache in upcoming GPUs is real and how it is made if it is. It will be separate cache chips since they can get much higher density with a cache optimized process. It is unclear whether the 512 MB is a single chip; 36 mm2 x 8 is 288 mm2 which is rather large. Cache can have redundant blocks to increase yield though. It could be a number of separate chips. If it is composed of tiny 64 MB die, then it would need 8 of them. For stacking with two gpu chiplets, then at least 2 or 4 die would be likely. A 128 MB die seems reasonable (possibly around 72 mm2).

This is relevant to Zen 4 and other AMD parts since the cache chips are likely to be used in Epyc parts; almost certainly in Bergamo. In fact, a lot of things are looking very similar. An Epyc IO die is 8 64-bit memory channels; 512-bit DDR for 1024-bits/clock internally. Current GPUs are 256-bit GDDR6, which I believe is QDR for an internal width of 1024 bits/clock also. Genoa seems to go up to 12 channel though. Perhaps next gen GPUs will go up to 384-bits. The CDNA GPUs have, I believe, 8 infinity fabric links, like an Epyc IO die. There is a lot of opportunity for at least shared IP here. Stacking may allow for actual shared devices. It may be possible to, for example, to have a 1024-bit unified memory controller chips stacked with separate die with the physical interfaces for the specific memory type or perhaps direct connected to a 1024-bit HBM stacks.

This is wild speculation, but I don’t doubt that AMD will take advantages of the synergies here. At a minimum, I think that the infinity cache chips will be used in cpu and gpu products. It likely isn’t coming until zen4c / Bergamo for CPUs though. I guess we get a preview of it with RDNA3.

 

[DrMrLordX]

@jamescox

You have a point but we do need to at least present a little context to prevent things from going too wildly off-topic; that being said, there haven't been any rumours of DDR4-capable AM5 products. The rumour-mill products were Warhol and Zen3D (which for a time were thought to maybe be the same thing). Both of those are/were AM4.

 

[andermans]

I'd think it would be more likely they bring out an AM4 variant with DDR4 than an AM5 variant with DDR4. If you're making a new IO die anyway that would avoid bifurcation for the AM5 platform and I'd guess AM4 is supportable with such an IO die as well.

 

[CakeMonster]

When unfounded rumors are less confusing than posts in this thread

 

[turtile]

That is why I suspect a much more limited release with Zen 4 than with Zen 3. I could be wrong, but their absolute best option is to keep most of the volume on N7 or N6 until Apple’s volume sales leave N5. They can do this by initially restricting Zen 4 to low volume, high margin parts.

How it looks today:

N7 - Milan, Milan-X, Vermeer, Zen3D (also Zen 2 parts), RDNA, RDNA2, etc.

What the future could look like:
N7 - Milan, Milan-X, Vermeer, Zen3D
N6 - Rembrandt, Navi33/34
N5 - Genoa, Navi31, Raphael, Navi31/32

I don't think this has anything to do with supply but rather cost. AMD could use 5nm at the same time as Apple if they gave TSMC the money to build out the capacity. This is why I also don't believe AMD waits for Apple due to capacity. They wait for Apple to make it cheaper.

This is why we don't have a low-cost line of Zen 3. It's cheaper to sell Zen 2 as the low-end because the die is smaller. Zen 3 is used in the mobile market because AMD needs to grab market share there.

If the rumors of AMD using Samsung 3nm are true, it's very likely that this will be for the low-end APU line and possible low-end GPUs. Not because it's better than TSMC N5P, but because it's cheaper.

 

[DisEnchantment]

I don't think this has anything to do with supply but rather cost. AMD could use 5nm at the same time as Apple if they gave TSMC the money to build out the capacity. This is why I also don't believe AMD waits for Apple due to capacity. They wait for Apple to make it cheaper.

This is why we don't have a low-cost line of Zen 3. It's cheaper to sell Zen 2 as the low-end because the die is smaller. Zen 3 is used in the mobile market because AMD needs to grab market share there.

If the rumors of AMD using Samsung 3nm are true, it's very likely that this will be for the low-end APU line and possible low-end GPUs. Not because it's better than TSMC N5P, but because it's cheaper.

It seems going forward, TSMC is seeking some downpayment from its top customers, which would probably help fund their 30 Billion USD yearly investment for 2022/23/24

AMD paid a around 355 Million last Quarter to improve supply for future products. If this continues, which it seems to be the trend, it will be more than 1.5 Billion USD prepayment in 1 FY.

https://ir.amd.com/sec-filings/filter/quarterly-filings/content/0000002488-21-000178/0000002488-21-000178.pdf

Prepaid long-term supply agreements relate to payments made to vendors to secure long-term supply capacity

It should improve supply going forward, instead of waiting for what is left over. As per the filing this is not related to the ATMP JV.

Additionally, as per ASML official data they mentioned all NXE3400B in the field have been upgraded to NXE3400C which improved throughput by 30%.

It’s worth noting that foundries that acquired the prior revisions of the machine (e.g., NXE:3400B) have all been upgraded to the 3400C as well. By the start of Q1 2021, there were 85 EUV machines installed in the field.

[Paywalled]

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

A look at the current state of EUV machines, the new NXE:3600D, and EUV pellicle readiness and industrialization.

fuse.wikichip.org

All new machines delivered now are the NXE3600D, which improved throughput even further, but those machines are expected to come online starting H2 next year.

There will be more capacity, but we are not due for a foundry update from TSMC until another 2Qs.
But needless to say, small players relying on Cybershuttle TOs will have basically zero wafers unless they are on older nodes.

 

[jpiniero]

This is why we don't have a low-cost line of Zen 3. It's cheaper to sell Zen 2 as the low-end because the die is smaller.

No it's because there are no chiplets left after Milan and higher end desktop.

 

[DrMrLordX]

No it's because there are no chiplets left after Milan and higher end desktop.

How many wafers is AMD committing to Zen2 at this point anyway, except for long-term delivery contract sales?

 

[Hans Gruber]

I am not worried about AMD right now. I think they need to make the AM5 platform compatible with DDR4 and DDR5 memory. I think they need to make sure the next memory controller has no mhz limitations like is previous ryzen CPU limitations on the ram speed.

 

[Joe NYC]

AM4 will be around for a while yet. There has been talk of 8 to 9 month delays with DDR5 due to shortages of the power management chips. With all of the delays, I would guess that anything using DDR5 might be a year away from any serious ramp. Genoa is supposed to be coming in 2022, but it may actually be held back by memory availability.

I would disagree here. The biggest server OEMs and hyperscalers get their DDR5 without any scalper middlemen, that may plague consumer market.

And it will be just a question of quantities and Milan vs. Genoa breakdown.

Granted, these are different process nodes, but if AMD has a surplus (slow uptake) in one area, it can shift wafers to another area, with insatiable demand - GPUs. Once N31 and N32 are production worthy, AMD can make more of those, since they use different memory...

I don’t think it is much of an issue that AMD didn’t release the v-cache parts. In fact, I think it is better that they didn’t. Intel takes the lead in some things, but it isn’t a clear victory due to the power consumption.

There is a huge installed base of Intel CPUs users, who were holding out so long for a worthwhile upgrade that they were almost ready to switch to AMD. And AMD gave them a reason (excuse) to stay with Intel - without feeling like an idiot.

Rushing out to release the v-cache would make it look like intel’s part is more competitive than it actually is. There are a bunch of people saying AMD must respond, but I would say that it actually looks better if they don’t. AMD is going to be selling everything they can make for a while yet regardless.

AMD has followed a wise strategy of staying in every market they have long term desire to grow in, despite the fact that there are silicon shortages, despite the fact that there is an opportunity cost for staying in market segments (GPUs, consloes for example) that may be le less profitable today than other ones.

In light of that, the retreat from high end of the desktop segment is not outright destruction of one part of AMD's TAM, but it makes is it highly uphill battle to realize more market share in desktop. Full year wasted, until Raphael, Zen 4 is released a year from now.

I haven’t been following Intel parts since I will almost certainly be buying AMD, but I don’t think Intel will really have a response to the v-cache parts and I think they will likely take the lead in most things, and for certain applications, the lead could be very large. Some applications will get a massive speed-up with that large of cache.

TLDR of that is AMD could have had a point from a tie in gaming, with Zen3d.

But by postponing the release of Zen 3D, the complete focus of this year's big hardware review season is a big fat L for AMD. And AMD will not recover from the loss by announcing Zen3d desktop when no one is paying attention. It will be a year until we have a similar attention to CPUs with Zen 4 generation release vs. Raptor Lake from Intel.

Another way to look at it, AMD could have still been in gaming leadership with Zen3D (by getting a tie in the reviews) with just a single stack of L3. By early next year, that single stack of L3 may be a yawn. And at this time, AMD / TSMC may not have a solution for the challenge of > 1 layer of V-Cache yet.

If your original point stands that DDR5 will be a problem throughout 2022, and it slows Zen 4 adoption, AMD could benefit from yet another bump to Zen 3 generation, by giving it another upgrade with multiple levels of V-Cache in H2 2022.

But, it is not like the competition is going to be running away, due to DDR5. Sapphire Rapids is DDR5 only, so DDR5 shortage would affect it as much as it would affect Genoa.

 

[uzzi38]

I am not worried about AMD right now. I think they need to make the AM5 platform compatible with DDR4 and DDR5 memory. I think they need to make sure the next memory controller has no mhz limitations like is previous ryzen CPU limitations on the ram speed.

1st won't happen. DDR5 only.

 

[Joe NYC]

AMD launching Zen3D in November 2021 or January 2022 doesn't really make much difference. Not that this is the Zen3D thread or anything, ya know.

When they launch AM5 + Raphael is going to be a much bigger deal.

I agree on Raphael. For volume segment of laptops, Raphael will be much bigger deal than than either Zen3D and Zen4 in desktops in 2022.

But by launching in H1 2022, do you think Raphael will face any problems with anticipated DDR5 shortage?

AMD could solve / side step it by getting LPDDR5 directly from the memory makers and incorporating it into the MCM...

 

[uzzi38]

AM4 will be around for a while yet. There has been talk of 8 to 9 month delays with DDR5 due to shortages of the power management chips. With all of the delays, I would guess that anything using DDR5 might be a year away from any serious ramp.

Sure, I agree with this bit pretty much all around. And at the end of the day, we already know that DDR5 production is only expected to outstrip that of DDR4 by the end of 2023.

Genoa is supposed to be coming in 2022, but it may actually be held back by memory availability.

No? Why would Genoa of all things be delayed by DDR5 shortages? It's the highest performance and if nothing else going to be one of the highest margin products utilising DDR5. It's like the least likely thing to get delayed.

 

[uzzi38]

How it looks today:

N7 - Milan, Milan-X, Vermeer, Zen3D (also Zen 2 parts), RDNA, RDNA2, etc.

What the future could look like:
N7 - Milan, Milan-X, Vermeer, Zen3D, Barcelo (Cezanne)
N6 - Rembrandt, Navi33/34, N31/N32 MCDs, Raphael IOD, Genoa IOD
N5 - Genoa CCDs, Raphael CCDs, Navi31/32 GCDs

FTFY. I think that should cover everything?

 

[Joe NYC]

I can’t keep track of all of the code names floating around, so I may be missing things, but I have wondered if a zen 4 chiplet might get paired with an older IO die if the DDR5 ramp turns out to be a disaster.

My guess is that AMD did not build downward compatibility into the Zen 4 chiplet. I think it is going to be tightly coupled link between Zen 4 CCD and IOD. It may incorporate technologies that were not available in Zen2/3 gen IO die.

Even if the flexibility may be there to make this real (Zen 4 Genoa with DDR4), DDR5 shortage will be short term and will be resolved. The extra cost of fragmentation of the platform would stay...

AMD has a lot of options with the level of modularity in their architecture. I suspect that the v-cache parts may have been intended for server only, but the cost made them reasonable for higher end desktop parts. The Zen X3D parts are already extending AM4 for about 2 extra years. With the extremely large cache, DDR5 bandwidth will be less important anyway. I don’t know if it is clear yet wether Zen X3D is just the original Zen 3 die or if it has some other updates. I am thinking that Zen 3+ is a different die, but I haven’t had time to look up much about it. They seem like they would have been parallel projects, so we might see 2 different products extending AM4.

Since the release of Zen3D in form of MilanX is coinciding with B2 stepping coming to market, it could be a coincidence, but more likely, there is a causation. Meaning, maybe Zen3D needed that B2 stepping to work with V-Cache, perhaps Zen3 B0 stepping was not quite fully tested and optimized for V-Cache.

I don't think these were parallel project, I think they were sequential. I think B2 stepping is the new Zen 3 die, serving both V-Cache and non-V-Cache processors.

Also, to get an idea of what is going on at AMD, you have to look at all of their parts. There is a lot of shared IP and possibly shared die going forward. We still don’t know if the rumored 512 MB infinity cache in upcoming GPUs is real and how it is made if it is. It will be separate cache chips since they can get much higher density with a cache optimized process. It is unclear whether the 512 MB is a single chip; 36 mm2 x 8 is 288 mm2 which is rather large. Cache can have redundant blocks to increase yield though. It could be a number of separate chips. If it is composed of tiny 64 MB die, then it would need 8 of them. For stacking with two gpu chiplets, then at least 2 or 4 die would be likely. A 128 MB die seems reasonable (possibly around 72 mm2).

One of the early rumors I came across some months ago that MCD (which apparently stands for multi-cache die) and can act as a silicon bridge with cache will possibly be used in parallel, depending on the final product. So Navi31 could have 2 or 4 of them in parallel, and Navi 32 could have 1 or 2.

Another possibility is that it will be just one of them and it will use stacking to achieve the higher SRAM capacity.

This is relevant to Zen 4 and other AMD parts since the cache chips are likely to be used in Epyc parts; almost certainly in Bergamo. In fact, a lot of things are looking very similar. An Epyc IO die is 8 64-bit memory channels; 512-bit DDR for 1024-bits/clock internally. Current GPUs are 256-bit GDDR6, which I believe is QDR for an internal width of 1024 bits/clock also. Genoa seems to go up to 12 channel though. Perhaps next gen GPUs will go up to 384-bits. The CDNA GPUs have, I believe, 8 infinity fabric links, like an Epyc IO die. There is a lot of opportunity for at least shared IP here. Stacking may allow for actual shared devices. It may be possible to, for example, to have a 1024-bit unified memory controller chips stacked with separate die with the physical interfaces for the specific memory type or perhaps direct connected to a 1024-bit HBM stacks.

This is wild speculation, but I don’t doubt that AMD will take advantages of the synergies here. At a minimum, I think that the infinity cache chips will be used in cpu and gpu products. It likely isn’t coming until zen4c / Bergamo for CPUs though. I guess we get a preview of it with RDNA3.

I am not sure if it was officially announced, but I think Genoa and Bergamo will share the SP5 socket. So it will probably make sense for Bergamo to support full 12 memory channels, so that the CPUs are swappable.

My thinking on Bergamo is that it is almost a Zen 4.5. The design had a much later start than Genoa, but sharing so much of the common IP allowed it to launch just ~3 quarters after Genoa, and one of the advantages is that being socket compatible could have cut another 2-3 quarters from validation.

Internally, Bergamo could be a different beast all together. Chiplet interconnect could have been swapped to much higher performance, lower power, lower latency, the core and CCD optimization de-emphasized single core performance, since the CCD will unlikely be shared with high end desktop, and instead prioritized being in the optimal zone of clock speed for the process technology, where the efficiency is the highest.

Having started so much later than Genoa gave the Bergamo team opportunities to incorporate very latest feedback from Zen being in the field and from the latest process technology and packaging / interconnect technologies. It could even mean that Genoa may be N5 and Bergamo N4.

 

[Joe NYC]

FTFY. I think that should cover everything?

Agreed with the corrections.

It's just missing the V-Cache die. Is that going to be N7 or N6? N6 would be consistent with expectations of MCD die.

 

[DrMrLordX]

But by launching in H1 2022, do you think Raphael will face any problems with anticipated DDR5 shortage?

We have no idea when Raphael will launch. Also there doesn't appear to be a shortage of DDR5 yet. I would expect production to move away from DDR4 and towards DDR5 in the months to come. Genoa and Sapphire Rapids will drive demand for it, as well Alder Lake.

 

[xilli_fiberbit]

It's a shortage of PMIC power management chip which is needed to build the DDR5 memory module, because this chip is not anymore on motherboard with DDR5

 

[DrMrLordX]

It's a shortage of PMIC power management chip which is needed to build the DDR5 memory module, because this chip is not anymore on motherboard with DDR5

If that proves to be a problem, it will cause trouble for far more than just Raphael.

 

[Joe NYC]

We have no idea when Raphael will launch. Also there doesn't appear to be a shortage of DDR5 yet. I would expect production to move away from DDR4 and towards DDR5 in the months to come. Genoa and Sapphire Rapids will drive demand for it, as well Alder Lake.

Sorry, I got the painters confused. I meant Rembrandt (not Rafael), which is rumored to be launching in Q1 or H1 2022, on a DDR5 platform...