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Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 6000)

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What do you expect with Zen 4?


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Ajay

Diamond Member
Jan 8, 2001
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Rough calculation using TSMC's numbers would say 100mm2 N6 dies would have roughly similar xtor count as 70mm2 N5 dies, (~40% bigger but~45% less dense), advantage being that there are lots more of N7/N6 wafers, around 200K wpm lets say.
The rub here is that TSMC's earlier estimate of ~40-45% area reduction for N5 aren't panning out in real silicon; otherwise it would be a great node to target. I have yet to find much in the way of updated details on N6 in terms of relative clocks, power and area. This means that AMD must have faced some challenging decisions 2-3 years ago when targeting Zen4 physical design. If they choose 5nm, then they must be scrambling to reach their adjust their performance and die size targets. May you live in interesting times!

There also is the issue of Intel buying 180k N6 wafers in 2021.
 

DisEnchantment

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Mar 3, 2017
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The rub here is that TSMC's earlier estimate of ~40-45% area reduction for N5 aren't panning out in real silicon; otherwise it would be a great node to target. I have yet to find much in the way of updated details on N6 in terms of relative clocks, power and area. This means that AMD must have faced some challenging decisions 2-3 years ago when targeting Zen4 physical design. If they choose 5nm, then they must be scrambling to reach their adjust their performance and die size targets. May you live in interesting times!

There also is the issue of Intel buying 180k N6 wafers in 2021.
1606848282514.png

Last year, TSMC announced the N6 node. This is an EUV-based node, but unlike N7+ which is entering its 2nd year of production, N6 is designed to be the easy migration path from N7 as its design rules are fully compatible with N7. In fact, TSMC considers N6 to be part of the “N7 family”. N6 is said to provide around 15-20% higher density with improved power consumption compared to N7, albeit no iso-power or speed comparisons where provided. We believe the density gains are obtained from switching from double diffusion breaks to a single isolation line. TSMC did note that N6 has 1 more EUV layer compared to N7+. TSMC reported that N6 is on track for risk production in the first quarter of this year with volume production expected before the end of the year. The 7 nm family is expected to continue to contribute more than 30% of wafer revenue in 2020.

TSMC's numbers (real density is much lower)
N7 -> N5 1.8x density gain
N7 -> N6 1.2x density gain
N6 -> N5 1.5x (estimate)
TSMC considers N6 to be part of N7 family.
What is interesting is that same design rules from N7 i.e. Zen3. If we keep iso performance (Zen3 transistor performance is good already, 5+ GHz) the power should go down a bit for N6.

Even if we assume 25% of TSMC allocation for N5, that would currently be at best 12-14K wpm which is fairly low, compared to AMD's 45K wpm in Q4 20. In 2021 N7/N6 will be quite abundant simply because there are many fabs, 4 fabs of N7 vs 1 fab for N5. New one will come online but that is late 2021 or early 2022 and targeted for N3.
15-20K wpm of N5 end of 2021 is just way too low, unless AMD can get 40-50% of N5 allocation which will not happen.

Quite a dilemma, build all on N5 or on N6 or both? They could build an IOD which can take either N5 or N6 chips. And hopefully move on to N6 as well for the rest of the products not on N5 instead of sticking with current process which would be 3.5 years old by end 2021
But I do hope they invest more transistors per core.
 
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Ajay

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Jan 8, 2001
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TSMC's numbers (real density is much lower)
N7 -> N5 1.8x density gain
N7 -> N6 1.2x density gain
N6 -> N5 1.5x (estimate)
TSMC considers N6 to be part of N7 family.
What is interesting is that same design rules from N7 i.e. Zen3. If we keep iso performance (Zen3 transistor performance is good already, 5+ GHz) the power should go down a bit for N6.

Even if we assume 25% of TSMC allocation for N5, that would currently be at best 12-14K wpm which is fairly low, compared to AMD's 45K wpm in Q4 20. In 2021 N7/N6 will be quite abundant simply because there are many fabs, 4 fabs of N7 vs 1 fab for N5. New one will come online but that is late 2021 or early 2022 and targeted for N3.
15-20K wpm of N5 end of 2021 is just way too low, unless AMD can get 40-50% of N5 allocation which will not happen.

Quite a dilemma, build all on N5 or on N6 or both? They could build an IOD which can take either N5 or N6 chips. And hopefully move on to N6 as well for the rest of the products not on N5 instead of sticking with current process which would be 3.5 years old by end 2021
But I do hope they invest more transistors per core.
Thanks for all the info, I guess I should have used Google instead of DuckDuckGo, lol!

I think it might be telling that TSMC will have only one 5N Fab. I wish we better knew their build out plans (maybe I should listen to the last earnings call). As you point out, 5N just doesn't have the capacity that AMD will need. Since N6 is built on N7 tooling + EUV, I would hope for better efficiency, even though the xtor size appears to remain the same (CPP and MMP). Better development tools must be improving circuit placement and routing. Still, if AMD wants to continue to improve perf/clock they will need, at the very least, additional xtors and more metal routing to truly widen the front end. If AMD is going big or going home, then a 12 core CCX would increase the die size quite a bit - I don't know if they have the volume yet to add a third die to their product mix (monolithic 8c, 8c chiplet and 12c chiplet). I'd be surprised if Zen4 is on 7N, so AMD must have picked N6 or N5, I think they will need some assist from process to hit any increased performance goals. I'm guessing we'll be waiting a while for any useful leaks given Zen3 just came out.
 

moinmoin

Platinum Member
Jun 1, 2017
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The outlook now though does not seem good with N5 for AMD.
With the situation as it is right now with wafer availability, would make AMD think hard about relying solely on N5 for their next gen products.
I disagree. AMD's big problem is not TSMC's capacity, it's that AMD's own projected demand (and as such the amount of wafers required to fulfill all demand) continually has been set far lower than it turned out in reality. This is not an issue specific to N7, N5 or any other node. TSMC's lead time is too long to react on short term, so AMD needs to be less financially conservative and take the risk ordering significantly more capacity at TSMC farther ahead.
 

LightningZ71

Senior member
Mar 10, 2017
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I feel that they will have to go in both directions: start producing Zen4 CCDs on N5 for premium products and also produce "ZEN3+" type products on N6. That will include a mobile SOC based on "ZEN3" and RDNA2 on N6, as well as subpremium CCDs on N6.

What about Samsung? We know that AMD has some sort of dealings with them as well.
 

DisEnchantment

Senior member
Mar 3, 2017
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I disagree. AMD's big problem is not TSMC's capacity, it's that AMD's own projected demand (and as such the amount of wafers required to fulfill all demand) continually has been set far lower than it turned out in reality. This is not an issue specific to N7, N5 or any other node. TSMC's lead time is too long to react on short term, so AMD needs to be less financially conservative and take the risk ordering significantly more capacity at TSMC farther ahead.
That was the case for N7 and acknowledged by AMD some time ago, but can't be the case for N5.
Most N7 fabs were retooled from 10nm and 8nm and they relied on DUV. And then eventually N7+ and N6 specific steps involving EUV were added later.
N5 uses EUV from the start and TSMC would need to build multiple fabs to reach N7 wpms.
So even if AMD tell TSMC they need 100k wpm now, they will not get 100k wpm by end of 2021. There are simply not enough EUV machines in existence. Samsung and Intel are literally fighting for the same equipment, and neither are short of money.
 
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burninatortech4

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I don't see core counts going up per-chiplet on AM5 or EPYC 7xx4. If EPYC/TR core counts increase it'll be because new packaging, pin changes, and/or IO die adjustments allow more chiplets per substrate.

For AM5 my guess is increase in pin count to enable DDR5 and PCI-e 5.0. I don't think we'll see FPGA's on consumer hardware for awhile longer. Also wouldn't be surprised to see more SoC features unlocked for consumer machines (why not use the NIC built into the SoC?!)
 

moinmoin

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That was the case for N7 and acknowledged by AMD some time ago, but can't be the case for N5.
Most N7 fabs were retooled from 10nm and 8nm and they relied on DUV. And then eventually N7+ and N6 specific steps involving EUV were added later.
N5 uses EUV from the start and TSMC would need to build multiple fabs to reach N7 wpms.
So even if AMD tell TSMC they need 100k wpm now, they will not get 100k wpm by end of 2021. There are simply not enough EUV machines in existence. Samsung and Intel are literally fighting for the same equipment, and neither are short of money.
You seem to assume that the existing capacity is already booked out for all eternity? Apple initially booking all capacity was the case with N7 as well, but its orders reduce over time (as it's past the point of stocking up for the respective big launch) as well as fab capacity is being increase. It may well be the case that that increase doesn't happen as fast with N5 as it did with N7 due to shortage of EUV lithography machines by ASML, but that shouldn't matter if(!) AMD secured sufficient wafers in time.

TrendForce even reports that N5's capacity utilization is not even at 100% as is anyway:
"With regards to the 5nm process technology, which is the most advanced node at the moment and which entered mass production in early 2020, Apple remains the sole client utilizing TSMC’s 5nm process after U.S. sanctions prohibited chip shipment to Huawei subsidiary HiSilicon. As such, despite Apple’s wafer input orders for its in-house-developed Mac CPU and FPGA accelerators used in servers, these wafer inputs are unable to completely make up for the leftover excess wafer capacities following HiSilicon’s departure. TSMC’s 5nm capacity utilization rate for 2H20 is therefore estimated to fall within the 85-90% range. Looking ahead to 2021, in addition to Apple’s 5nm+ wafer input for the A15 Bionic SoC, trial production will also kick off for a small batch of AMD 5nm Zen 4 CPUs. These products will help maintain TSMC’s 5nm capacity utilization rate at an 85-90% range next year."
 
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DisEnchantment

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You seem to assume that the existing capacity is already booked out for all eternity? Apple initially booking all capacity was the case with N7 as well, but its orders reduce over time (as it's past the point of stocking up for the respective big launch) as well as fab capacity is being increase. It may well be the case that that increase doesn't happen as fast with N5 as it did with N7 due to shortage of EUV lithography machines by ASML, but that shouldn't matter if(!) AMD secured sufficient wafers in time.

TrendForce even reports that N5's capacity utilization is not even at 100% as is anyway:
"With regards to the 5nm process technology, which is the most advanced node at the moment and which entered mass production in early 2020, Apple remains the sole client utilizing TSMC’s 5nm process after U.S. sanctions prohibited chip shipment to Huawei subsidiary HiSilicon. As such, despite Apple’s wafer input orders for its in-house-developed Mac CPU and FPGA accelerators used in servers, these wafer inputs are unable to completely make up for the leftover excess wafer capacities following HiSilicon’s departure. TSMC’s 5nm capacity utilization rate for 2H20 is therefore estimated to fall within the 85-90% range. Looking ahead to 2021, in addition to Apple’s 5nm+ wafer input for the A15 Bionic SoC, trial production will also kick off for a small batch of AMD 5nm Zen 4 CPUs. These products will help maintain TSMC’s 5nm capacity utilization rate at an 85-90% range next year."
I did read this and many others, and this is what piqued my interest today and posting my thoughts on the matter.
Early next year mainly Apple & QCM would not probably use up TSMC's capacity. This is what I believe would lead to under untilisation of TSMC's capacity for the whole year.
Zen4 and other products on next node would have to ramp by Q4 2021, going by AMD's cadence of 12-15 months, with a launch by Q1 2022. If no delays.

Now going by AMD's official projection of 30-40% CAGR (and they are beating projections, though not by much), I have doubts they will in a better position than what they are in today, supply wise in H1 2022. Just simply looking at TSMC's available capacity for N5 (from public info) if we assume a chunk of products will be on N5.
Which means a big chunk of products would be on an older node, or worse, they cut back on how much die space they allocate per core.
We have to keep in mind this is no trivial matter, For example, a 20% bigger CCD automatically means AMD have much lesser products to sell from the same raw materials they have.
This in my opinion is one of many factors like yields, costs, power etc, which influence how big the CCDs can be. I mean we can just look at AMD's competition whose initial goals for node advance is to make smaller dies for more profit.
Eventually the bean counters will decide, but it is a shame if the engineers would be constrained by such a thing.

What I would not like to see is that Architecture could be held back for lack of silicon real estate, and especially when we know that with N5 there are efficiency gains to be had which would make bigger dies even more feasible within the same power/thermal envelope. And TSMC saying yields essentially being same.
A 100mm2 N5 CCD would allow AMD's engineers 80% more transistors than Zen3 to work with. Maybe I am just being an engineer and maybe not too much for incrementalism. Especially in the light of other vendors being aggressive in this regards as well.
 

amrnuke

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Apr 24, 2019
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That was the case for N7 and acknowledged by AMD some time ago, but can't be the case for N5.
Most N7 fabs were retooled from 10nm and 8nm and they relied on DUV. And then eventually N7+ and N6 specific steps involving EUV were added later.
N5 uses EUV from the start and TSMC would need to build multiple fabs to reach N7 wpms.
So even if AMD tell TSMC they need 100k wpm now, they will not get 100k wpm by end of 2021. There are simply not enough EUV machines in existence. Samsung and Intel are literally fighting for the same equipment, and neither are short of money.
N6 uses EUV, so if AMD request 100K wafers of N6 or N5, if the limit is EUV machines, then that's that. Doesn't matter what they request, right? Or am I missing something here?
 

moinmoin

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Jun 1, 2017
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N6 uses EUV, so if AMD request 100K wafers of N6 or N5, if the limit is EUV machines, then that's that. Doesn't matter what they request, right? Or am I missing something here?
My understanding is N6 is an extension of the existing N7 fabs. N5 is a different fab location altogether, can't move EUV lithography machines between them at will. ;)
 
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DisEnchantment

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N6 uses EUV, so if AMD request 100K wafers of N6 or N5, if the limit is EUV machines, then that's that. Doesn't matter what they request, right? Or am I missing something here?
Yes, N6 is using EUV, there are 5 layers which relies on EUV lithography and the rest is DUV (compared to 4 layers for N7+) . N5 has 3-4 times more EUV layers than N6 (exact number of layers value witheld by TSMC). So they need considerably more EUV machines for N5 to maintain same wpm.
They basically added steps involving EUV lithography in the mix with the DUV lithography for N7 to turn it to N7+/N6. But plain N7 started off from reworked 8nm/10nm processes. Hence a lot more machines available,
 
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moinmoin

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I did read this and many others, and this is what piqued my interest today and posting my thoughts on the matter.
Early next year mainly Apple & QCM would not probably use up TSMC's capacity. This is what I believe would lead to under untilisation of TSMC's capacity for the whole year.
Zen4 and other products on next node would have to ramp by Q4 2021, going by AMD's cadence of 12-15 months, with a launch by Q1 2022. If no delays.

Now going by AMD's official projection of 30-40% CAGR (and they are beating projections, though not by much), I have doubts they will in a better position than what they are in today, supply wise in H1 2022. Just simply looking at TSMC's available capacity for N5 (from public info) if we assume a chunk of products will be on N5.
Which means a big chunk of products would be on an older node, or worse, they cut back on how much die space they allocate per core.
We have to keep in mind this is no trivial matter, For example, a 20% bigger CCD automatically means AMD have much lesser products to sell from the same raw materials they have.
This in my opinion is one of many factors like yields, costs, power etc, which influence how big the CCDs can be. I mean we can just look at AMD's competition whose initial goals for node advance is to make smaller dies for more profit.
Eventually the bean counters will decide, but it is a shame if the engineers would be constrained by such a thing.

What I would not like to see is that Architecture could be held back for lack of silicon real estate, and especially when we know that with N5 there are efficiency gains to be had which would make bigger dies even more feasible within the same power/thermal envelope. And TSMC saying yields essentially being same.
A 100mm2 N5 CCD would allow AMD's engineers 80% more transistors than Zen3 to work with. Maybe I am just being an engineer and maybe not too much for incrementalism. Especially in the light of other vendors being aggressive in this regards as well.
I wrote somewhere else on here sometime that with the CAGR AMD is "projecting" so far it would take AMD 10 years to reach the revenue Intel has today. And I think that's the point, AMD plays it safe regarding growth. And that's a good idea since long term steady growth is better than a short term huge growth bump that's impossible to follow up on. And that growth is still plenty high by itself and as such looks good for the stocks market.

In that regard I don't think engineers are constricted by any die size factor or similar, very likely even technical design decisions are made constructing a path of steady growth gen per gen. The only unnecessary limitation AMD faces in my opinion is wafer shortage, and that's something that's fully its own fault, messing up the projection of demands to the point of continually being unable to fulfill it at this point. But maybe that's part of the plan of keeping CAGR stead(il)y (lowish)? ¯\_(ツ)_/¯
 

DisEnchantment

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I wrote somewhere else on here sometime that with the CAGR AMD is "projecting" so far it would take AMD 10 years to reach the revenue Intel has today. And I think that's the point, AMD plays it safe regarding growth. And that's a good idea since long term steady growth is better than a short term huge growth bump that's impossible to follow up on. In that regard I don't think engineers are constricted by any die size factor or similar, very likely even technical design decisions are made constructing a path of steady growth gen per gen. The only unnecessary limitation AMD faces in my opinion is wafer shortage, and that's something that's fully its own fault, messing up the projection of demands to the point of continually being unable to fulfill it at this point. But maybe that's part of the plan of keeping CAGR stead(il)y (lowish)? ¯\_(ツ)_/¯
It is not like they have a choice. Intel has around 400K+ wpm of 10/14nm alone, TSMC has 1/2 of that, and that too taking into consideration all the myriad of wafers from 28/16/12/7nm etc. Out of all that AMD gets like 20-25%.
Francois Piednoel made a calculation of this on twitter and he is wrong on many things but I think he is right on this. He basically says AMD can never take significant marketshare from Intel :grinning:

Someone wrote something like this in the other thread, Available but mediocre or barely available but top notch in everything. As an enthusiast and engineer it is quite hard to be interested in the former.
 

moinmoin

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It is not like they have a choice. Intel has around 400K+ wpm of 10/14nm alone, TSMC has 1/2 of that, and that too taking into consideration all the myriad of wafers from 28/16/12/7nm etc. Out of all that AMD gets like 20-25%.
Francois Piednoel made a calculation of this on twitter and he is wrong on many things but I think he is right on this. He basically says AMD can never take significant marketshare from Intel :grinning:

Someone wrote something like this in the other thread, Available but mediocre or barely available but top notch in everything. As an enthusiast and engineer it is quite hard to be interested in the former.
I don't think market share is of any real importance. That will come naturally if you got a good product that is in demand. And AMD's products are all increasingly in demand, and AMD fails to follow suit with the supply. Slow growth in that regard is a good thing as it allows TSMC to plan increasing future capacity accordingly, just like TSMC grew in size fulfilling Apple's increasing demands. But to get back to the main point I keep harping on: For that to happen AMD needs to gets its projections of expected demands in order to begin with, they are clearly off by a magnitude or something right now. :sweatsmile:
 

LightningZ71

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Mar 10, 2017
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It's too bad that Samsung can't seem to keep pace with TSMC. It would be good for AMD to have a second source supplier to bid against TSMC with. I still think that competitive pressures are going to force AMD onto N6 with at least some of their products. They're already experimenting with market acceptance of two different Zen cores in the same processor family (5xxxu).
 

Gideon

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Nov 27, 2007
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It is not like they have a choice. Intel has around 400K+ wpm of 10/14nm alone, TSMC has 1/2 of that, and that too taking into consideration all the myriad of wafers from 28/16/12/7nm etc. Out of all that AMD gets like 20-25%.
Francois Piednoel made a calculation of this on twitter and he is wrong on many things but I think he is right on this. He basically says AMD can never take significant marketshare from Intel :grinning:

Someone wrote something like this in the other thread, Available but mediocre or barely available but top notch in everything. As an enthusiast and engineer it is quite hard to be interested in the former.
The TSMC numbers seem a bit on the low side. About 1/3 of their wafers were were 28nm - 7nm in 2019. Considering the revenue surge in Q2 and Q3 and the amount of it coming from 7nm I seriously doubt it's as low now. Even if it is, they shipped ~3M wafers total in Q2 (based on previous wikichip link). Using 2019 breakdown, that's still at least 330K wpm not 200K wpm. Considering that 5nm is seriously ramping up as well as all the crazy demand for 7nm now I don't think it's that low now (out of Q3 revenue 5nm was 8% , 7nm was 35% and 16nm was only 18%) . Though yeah, in regards of wafers only a fraction of that is 7nm/5nm.

TSMC's throughput would certainly be a concern, if AMD would need to take all of Intel's market share, but that's IMO not a really realistic scenario. I can see them taking 30-50% though.

AMD also has Samsung and Global-foundries to draw from for all but the most critical chiplets of their design. After all the I/O die on Rome is about the same size as 8 CCD's combined, For client I/O die it's almost as big as 2x CCD. When also factoring in yields and repurposing, they need considerably less than half of Intel's 14nm throughput to match the same amount of SKUs.


Overall I guess we'll have to see how forward looking AMD was with their plans. I could see Van Gogh (for instance) being designed on on Samsungs 7nm not TSMC. That would fit nicely with a few known facts (if this roadmap is accuarate):
  • It's strictly a mobile-only part (LPDDR4X and 5 only) therefore it doesn't need to go all that far on the power-efficiency curve.
  • It uses Zen2 cores (Zen 3 most certainly would not have been ready for foundry transition)

APUs like that could feed the majority of the laptop market (volume-wise) and don't necessarily need to be built on TSMC. The halo-ones probably have to, but these are of limited volume
 
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Ajay

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Jan 8, 2001
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Even if it is, they shipped ~3M wafers total in Q2 (based on previous wikichip link). Using 2019 breakdown, that's still at least 330K wpm not 200K wpm. Considering that 5nm is seriously ramping up as well as all the crazy demand for 7nm now I don't think it's that low now (out of Q3 revenue 5nm was 8% , 7nm was 35% and 16nm was only 18%) . Though yeah, in regards of wafers only a fraction of that is 7nm/5nm.
FWIW, revenues for N7, and especially N5 are disproportionate to wafer volume due to their much higher cost.

I can't figure out what the heck Warhol would be on N7 since it's still Zen3, unless it's on some modified N7 process like EUV for a bit more performance. If Warhol is for real, then AMD is taking longer developing Zen4, or needs to wait longer till N5P is up and running in volume.
 

Gideon

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FWIW, revenues for N7, and especially N5 are disproportionate to wafer volume due to their much higher cost.

I can't figure out what the heck Warhol would be on N7 since it's still Zen3, unless it's on some modified N7 process like EUV for a bit more performance. If Warhol is for real, then AMD is taking longer developing Zen4, or needs to wait longer till N5P is up and running in volume.
Yeah i even mentioned the fact that this is disproportional.

Regarding Warhol, my guess its just the same Zen3 chiplets on AM5, new packaging (possibly 2.5D) and new I/O die (with DDR5 support). Extracting more performance from the I/O and uncore side.

EDIT:
Spelling (sorry I tend to write type-messes on my phone)
 
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