- Jan 8, 2001
The rub here is that TSMC's earlier estimate of ~40-45% area reduction for N5 aren't panning out in real silicon; otherwise it would be a great node to target. I have yet to find much in the way of updated details on N6 in terms of relative clocks, power and area. This means that AMD must have faced some challenging decisions 2-3 years ago when targeting Zen4 physical design. If they choose 5nm, then they must be scrambling to reach their adjust their performance and die size targets. May you live in interesting times!Rough calculation using TSMC's numbers would say 100mm2 N6 dies would have roughly similar xtor count as 70mm2 N5 dies, (~40% bigger but~45% less dense), advantage being that there are lots more of N7/N6 wafers, around 200K wpm lets say.
There also is the issue of Intel buying 180k N6 wafers in 2021.