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Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 6000)

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What do you expect with Zen 4?


  • Total voters
    168

jpiniero

Diamond Member
Oct 1, 2010
8,397
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Also this is not an either/or, AMD can still (continue to) offer packages with fewer cores that as a result have a bigger TDP headroom for higher frequencies. All of its top end products are "hampered" by the TDP limit (even consumer chips like 3950X and 5950X), but as a result those are also more energy efficient, that's part of the balance customers can choose between.
AMD could keep the AM5 core count static while increasing core counts on Threadripper and Epyc. Because of Intel's big.LITTLE, I could see AMD wanting to go more than 8 cores on mobile but 16 cores on desktop will be good for awhile.
 

soresu

Golden Member
Dec 19, 2014
1,491
703
136
When filming the Matrix, when the actors say "There is no spoon," they are speaking the truth. It was added in CGI later.
Makes sense, that famous shot of the red and blue pills in separate lenses of Morpheus's specs was done in post too.
 

soresu

Golden Member
Dec 19, 2014
1,491
703
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AMD could keep the AM5 core count static while increasing core counts on Threadripper and Epyc. Because of Intel's big.LITTLE, I could see AMD wanting to go more than 8 cores on mobile but 16 cores on desktop will be good for awhile.
I personally think this will be the way they will go, keeping AMx for low to high end APU's and TRx for enthusiast/creator core counts.

Having said that, they will need a chunky GPU in AMx to justify that - 32 CU at least, preferably with HBM2/3.
 

eek2121

Senior member
Aug 2, 2005
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AMD could have a hybrid chip with a smaller 5nm die (or 2) and a larger 7nm die. It's curious that their previous roadmaps said nothing about desktop 5nm...
 

inf64

Diamond Member
Mar 11, 2011
3,060
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I expect that Zen4 is very similar project to Zen2. It will widen the FP and L/S by 2x, add (most likely) 2x the cores per chiplet. I hope that AMD will go Zen3 route with regards to CCX and share a huge pool of (64MB?) L3 cache among 16 Zen4 cores. Similarly to Zen2, I think they will aim at around 15ish% IPC jump versus Zen3 - this would leave Zen5 with very optimistic (but obviously achievable) target of ~21% IPC improvement coming from Zen4, if they were to keep the 40% increases between their "tocks" (EX->Zen1; Zen1->Zen3 ; Zen3->Zen5?).
There are some rumors of further chiplet design evolution and some possible massive (L4?) caches, new memory controller + DDR5 support, shrinking of the IOD etc. Zen4 definitely looks like the next big core count increase and a major platform update.
 

DisEnchantment

Senior member
Mar 3, 2017
647
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AMD could have a hybrid chip with a smaller 5nm die (or 2) and a larger 7nm die. It's curious that their previous roadmaps said nothing about desktop 5nm...
AMD's patent for their hybrid chip is quite interesting. They rely on illegal instruction exception to wake up the big cores and transfer the register state to them and avoid depending on the scheduler like current hybrid designs. Sounds like a bad idea from security perspective on server chips though. So will be client only probably.
 

jamescox

Member
Nov 11, 2009
138
253
116
Yup. With AM5, I imagine they go larger on the socket size. Combined with process shrink to 5nm, we can still keep a lower transistor density while cramming a lot more on the chip. The other sockets I don't expect a significant change.

32c/64t 6950X
128c/256t 6990X
128c/256t or 128c/512t Epyc 7xx3

Fun times ahead when you consider the IPC/power consumption improvements expected.
I don't see why the package would need to be larger. I also doubt that they will scale the core counts that much for desktop parts. They might be able to double it again, but I don't think it is necessary for desktop parts. Not sure if you are being serious. It will not have enough memory channels to support huge core counts, although with enough cache that may not be an issue. Genoa will probably use chip stacking of some kind, so there may not even be a discrete IO die for Genoa. It could be an active interposer with cpu die stacked on top or some other form of chip stacking. TSMC has many different types of chip stacking available now or coming soon (posted several times somewhere here):


For Epyc, they may have a variant that actually stacks more than one cpu die on top of another or stacks cache with cpu die. TSMC has chip stacking tech that does not use micro solder balls which has better thermal characteristics than stacking tech with micro solder balls. They could easily make Epyc processors optimized for frequency with 1 or a small number of layers and other processors optimized for core count with mutiple layers of CPU die.

I don't know if they would have different stacked and non-stacked variants. Non-stacked variants would be cheaper with better thermal characteristics for low core count devices. If they use chip stacking for desktop parts, then the footprint may actually be significantly smaller than the current footprint for 2 cpu die and IO die, so the socket wouldn't need to be larger. They could also use LSI tech, which uses a smaller piece of silicon embedded in the package (with multiple die overlapping it) rather than a full interposer. In that case, the chips would be smaller and closer together. The smallest form factor (and most expensive), would be a full active interposer; circuitry to drive external interfaces, which require larger transistors, would be in the active interposer. It may still have some IO die stacked on top. You could perhaps have a memory controller chiplet with cache at 7 nm while the physical interface is in the active interposer.

If Genoa actually does use stacked cpu die then I would expect a significant core count increase would be possible. The IFOP (on package, 32-bit wide serdes at 4x IO die clock to roughly match 256-bit internal IO die pathways) would probably be replaced with vertical connections that could be ~ 1024 bits wide. A single HBM stack uses a 1024-bit interface. That would reduce latency and increase bandwidth significantly. It would also reduce power consumption significantly vs. what would be needed to achieve similar speeds with pcie-5 clocked serdes links.

Speculating about what route they will go when chip stacking is used is very difficult. They could have a wide range of Epyc products with many different types of chiplets, possibly HBM or even full HBM gpus integrated into the package. The area needed for the cpus could be quite small with different forms of chip stacking, so there could possibly be room for an HBM gpu on either side. Package power consumption would be very large and it may limit the size of gpu that could be used.
 

jamescox

Member
Nov 11, 2009
138
253
116
I expect that Zen4 is very similar project to Zen2. It will widen the FP and L/S by 2x, add (most likely) 2x the cores per chiplet. I hope that AMD will go Zen3 route with regards to CCX and share a huge pool of (64MB?) L3 cache among 16 Zen4 cores. Similarly to Zen2, I think they will aim at around 15ish% IPC jump versus Zen3 - this would leave Zen5 with very optimistic (but obviously achievable) target of ~21% IPC improvement coming from Zen4, if they were to keep the 40% increases between their "tocks" (EX->Zen1; Zen1->Zen3 ; Zen3->Zen5?).
There are some rumors of further chiplet design evolution and some possible massive (L4?) caches, new memory controller + DDR5 support, shrinking of the IOD etc. Zen4 definitely looks like the next big core count increase and a major platform update.
It will get difficult to scale the cache size larger without increasing latency. Some form of L4 may be more likely. I don't think they are going to jump to a 16 core CCX right after going to an 8 core. It may be possible that they would make a 16-core chiplet with 2 CCX on one die. I expect Zen 4 to be very similar to Zen3. Zen 3 is a new architecture, so I don't think we will see huge changes to most of the functionality. Using stacked chips allows for much higher bandwidth, so I wouldn't be surprised to see internal pathways widened significantly and much increased FP performance. Stacked chips can easily use 1024 bit links; a single HBM stack is 1024-bits, so I am wondering if internal paths will actually go up to 1024 bits to match.
 

eek2121

Senior member
Aug 2, 2005
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The desktop chip will probably be 6nm with a new 7nm IO die. Higher clocks and IPC along with new instructions.
 

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