Speeding up or widening the IF would be more costly power wise, as would using more cache (which looks set at 32MB from the screen grab).
Speeding up the IF at same or lower power may be possible by going 2.5D, i.e. using a silicon interposer for the interconnect (full or bridge/EMIB-style), unlike having the interconnect implemented in the courser package substrate, as it is.
Regarding cache size, the slide says 32+ MB. I guess they will use the slight density increase and power-efficiency improvement of the N7+ process to double it to 64 MB, primarily to compensate for an increase in L3 latency in the 8-core complex.
If they use the 2x4 topology I propose (in
the CCX thread), they may be able to offer two BIOS configurations for the chiplet, i.e. two separate 4-core CCXs (NUMA), each with a private 32 MB of low-latency L3 cache, or an 8-core CCX (UMA), with 64 MB of higher-latency L3 cache.