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Speculation: Ryzen 4000 series/Zen 3

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tamz_msc

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Jan 5, 2017
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Richie Rich

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Jul 28, 2019
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Wasn't that slide a leak from the UK conference that wasn't meant to go public?
That's why AMD disclosed all Zen3 uarch features at this presentation. They were so sure it will never leak to public. Haha. Clearly AMD is not as naive as you are. No offense.

We can be 100% sure about SMT2 mode for Zen 3 - doesn't matter if vanilla SMT2 or SMT4 uarch can run SMT2 mode.

The question is if completely new uarch will support SMT4 too. IMHO if AMD see some server benefits in SMT4, there is no better time to implement it than completely new uarch. Next opportunity would be next new uarch which might be Zen 6/7, quite too far. AMD had pretty good reason for implementing SMT4 in Zen3. Even it would be enabled for Epyc or special Epyc line up.
 

amd6502

Senior member
Apr 21, 2017
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A layman curiosity: SMT3 is possible? Three threads, an odd number instead of even?
There's no reason it wouldn't be possible. But if probably wouldn't be worth it. It's that number where you might as well stay at SMT2 or just jump to SMT4 capability and allow the user to select his preference (SMT0, SMT2, SMT3, or SMT4).
 

Thunder 57

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Aug 19, 2007
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That's why AMD disclosed all Zen3 uarch features at this presentation. They were so sure it will never leak to public. Haha. Clearly AMD is not as naive as you are. No offense.

We can be 100% sure about SMT2 mode for Zen 3 - doesn't matter if vanilla SMT2 or SMT4 uarch can run SMT2 mode.

The question is if completely new uarch will support SMT4 too. IMHO if AMD see some server benefits in SMT4, there is no better time to implement it than completely new uarch. Next opportunity would be next new uarch which might be Zen 6/7, quite too far. AMD had pretty good reason for implementing SMT4 in Zen3. Even it would be enabled for Epyc or special Epyc line up.
Will you admit you were naive when Zen 3 comes out and there is no SMT4? Honest question.
 

.vodka

Golden Member
Dec 5, 2014
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I feel like someone should post an ape of that old golden comment about Bulldozer IPC.

Zen3 SMT increases!

The more I post, the more SMT increases!
Leave that buried, please. No need to jinx Zen3, lol

or is it already with all the SMT4 talk? :eek:
 
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soresu

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Dec 19, 2014
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Leave that buried, please. No need to jinx Zen3, lol

or is it already with all the SMT4 talk? :eek:
I don't see that as a jinx at all, merely a show of AMD pushing forward aggressively.

I agree SMT4 seems pretty unlikely though
 

Richie Rich

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Jul 28, 2019
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SMT4 will likely appear with completely new uarch. This is Zen3 or next new uarch (Zen6? in 2023 assuming Mike T. Clark is the new uarch creator in AMD right now). AMD is pushing development forward aggressively and there was Jim Keller involved.... so IMHO SMT4 will appear with Zen3. I think those whispers from Moors Laws Dead might be eventually true no matter how crazy it sounds. With completely new uarch can happen a lot of crazy things.

Maybe AMD will rewamp Bulldozer uarch because they found a way how to make performace from those 2xALUs :D
 

uzzi38

Member
Oct 16, 2019
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SMT4 will likely appear with completely new uarch. This is Zen3 or next new uarch (Zen6? in 2023 assuming Mike T. Clark is the new uarch creator in AMD right now). AMD is pushing development forward aggressively and there was Jim Keller involved.... so IMHO SMT4 will appear with Zen3. I think those whispers from Moors Laws Dead might be eventually true no matter how crazy it sounds. With completely new uarch can happen a lot of crazy things.

Maybe AMD will rewamp Bulldozer uarch because they found a way how to make performace from those 2xALUs :D
The fact that MLiD has said it means there's like a 90% chance it won't happen. Give or take 10%.

Besides, silicon is out there already, it's not happening.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Not sure why people are insistent on seeing SMT4. The difficulties in making SMT work is in validation. With SMT4, it requires even more work while providing diminishing returns.

We're starting to get enough cores which also reduce the effectiveness of SMT even for multi-threaded applications. We know gains with extra logical threads are only true when the code can benefit from more threads than there are physical cores. This is the same reason why SMT for Intel dual cores were great on gaming, but reduced performance on the quad cores.

The difference with IBM's POWER chips are that they put in more than bare minimum necessary to specifically better gains for SMT. SMT on Intel/AMD processors use a mere ~5% of core area, meaning total die wise, its in the 1-2% range. On Power 5, SMT-specific enhancements caused the core area to balloon by 24%. That's a big amount, and something that can be used to increase ILP instead, which is far more relevant to areas Intel/AMD plays in.

See, for IBM that derives most of its benefits on selling software and hardware(including the CPU) tailored for that software, it makes sense to further optimize. It's SMT also tends to do very well in transactional database which is a big chunk of the market for them.

In the case of Intel/AMD they are selling chips all the way from 12mm thick ultrabooks to enthusiast gaming desktops and massive $200+ million HPC server clusters.
 

yeshua

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Aug 7, 2019
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What I'm personally looking forward to is the optimizations of the IO die and chipset in terms of idle power consumption (I don't understand how AMD is going to solve this issue in their Zen 2 based APUs unless they downgrade the PCI-E interface to version 3.0).

For some reasons the IO die on Ryzen 3000 CPUs is always active and consumes around 15W when paired with an X570 based motherboard whose chipset again in idle consumes around 10W which means we're looking at 25W of drain for this couple. Not a lot but when talking about millions of PCs which are usually idle, this results in millions of watts of energy wasted. I've seen no explanations of this strange behavior. The IO die aside Ryzen 3000 CPU are extremely power efficient and idle in less than 2W.
HWInfo-stock.png Artem S. Tashkinov
 

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IntelUser2000

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For some reasons the IO die on Ryzen 3000 CPUs is always active and consumes around 15W when paired with an X570 based motherboard whose chipset again in idle consumes around 10W which means we're looking at 25W of drain for this couple. Not a lot but when talking about millions of PCs which are usually idle, this results in millions of watts of energy wasted. I've seen no explanations of this strange behavior.
Can't say for the X570, why it uses so much power as its the first one with PCI Express 4.0. It could be that they simply didn't bother reducing idle power, or the design has issues. It could even be that there's something in the PCI Express 4.0 spec that works against low power states, but with it being the only implementation, we can't say for sure.

But the reason for the I/O chiplet using lot of power in idle is simply because its not monolithic. For desktops and servers, few extra W of power doesn't really matter when chiplet using MCM seems to be the way to increase core count with latest processes.

They might be able to get away with that approach in 45/55W H-class ships where performance is a priority but anything requiring remotely good battery life would need a monolithic chip.

The IO die aside Ryzen 3000 CPU are extremely power efficient and idle in less than 2W.
I assume you mean Ryzen 2000 here.
 
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ksec

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There are finite amount of application that would benefits from 64 Core SMT4. We are already running into issues on a 2S System with 128 Core, 256 Threads. And for majority of today's hyper scaler, they want to scale out, not scale up. And the 2S 128C / 256T System right now seems to be in a very good place.

Right now the thing that is missing is Software, and tools. Which is lacking compare to Intel's side. The Open Source community are working to improve this with great enthusiasm, I just wish AMD could spend a little more resources in this area.
 

amrnuke

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Apr 24, 2019
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We're going off topic here, but I'll bite as I do love this stuff.

How do they know he destroyed Iliad era Troy/Troia if he actually destroyed it?

Were there fragments that dated to the appropriate era in his excavated rubble or something?
@soresu Destroy is a strong word and I applied it too broadly. He destroyed the integrity of the Troy of the Iliad (Troy VI, ~1500 BC) layer. He had no permit from the Turkish government and did the excavations illegally. He also didn't document in any meaningful way the many other Troys that he dug through. In total he dug through Troy VII -> III before reaching what he claimed was the Troy of the Iliad, when in reality it was Troy II (~2300 BC). He even had the audacity to take the things he found, giving his wife some of the jewelry, adorning his house with artifacts, etc. Because of his stupidity, he permanently damaged the archaeological record of the site (illegally, mind you) while also being wrong about what he had "found."

Fortunately, they were able to go back and date and index the things he dug through, and while a fair amount of it was damaged or destroyed, they have since recovered a lot of good stuff.
 

soresu

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Dec 19, 2014
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I just wish AMD could spend a little more resources in this area.
It's my fervent hope that the successes of Zen, and (if we're lucky) the successes of RDNA will improve AMD's financials to the point where they can spend more than just a little more on software again.

It's tripped them up consistently in the professional GPU market until now, but there is only so much you can do on a limited budget I guess.
 
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moinmoin

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Jun 1, 2017
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I didn't notice, is the NIC on chip or still external?
The NIC is external since AMD owns no NIC IP. But that's not a chipset.

It's my fervent hope that the successes of Zen, and (if we're lucky) the successes of RDNA will improve AMD's financials to the point where they can spend more than just a little more on software again.

It's tripped them up consistently in the professional GPU market until now, but there is only so much you can do on a limited budget I guess.
I hope they push open source development even more. It's bad enough that open source software like compilers as GCC still don't make good use of the Zen capabilities.
 
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soresu

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I hope they push open source development even more. It's bad enough that open source software like compilers as GCC still don't make good use of the Zen capabilities.
The crazy thing is that Sony are still posting optimisations for Jaguar even now, I suspect the rapid iteration of Zen will cause some backlog in serious optimisation - the price of progress in a hardware oriented smaller company I guess.
 

soresu

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