Yes? Physics is a bitch. L2 takes more die space than L3, and as you may have noticed, having a lot of L3 with good prefetch units can do a lot of improve the performance of multicore CPUs in parallel workloads with lots of intercore communication. Which is one sort of workload for which Intel and AMD have optimized their CPUs. Compare that situation to Apple who exclusively uses their A-series SoCs in phones and tablets where bursty, single-threaded (or sparsely-threaded) applications predominate. There you have less likelihood of core->core writes, meaning maintaining cache coherency is less important (and therefore, shared L3 is less important). So Apple chose to spend a lot of die area on L2 that could have been spent elsewhere, or that could not have been spent at all (driving higher yields and/or lower costs per die). Apple has the freedom to charge insane amounts of money for their hardware, and they don't have any OEMs telling them to trim costs, since they provide all their own SoCs for their own designs from top to bottom.
This is redacted. Apple L2 is shared so it's working just like L3 of todays x86 designs. AMD does use L2 as last level cache with Jaquar, private L2 is just intermediate cache level to increase performance, which Apple yet don't use. But that's easy few percent of more performance for Apple if they also implement that. For low clock-targeted devices like Apple soc and AMD Jaquar that middle cache level won't bring as much performance advantage that designs prefer to save die space and not use it, but if Apple scales their clocks up they probably also will implement that 3-level cache system.
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