Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[Kepler_L2]

This is what Grace Superchip was until using NVLink-C2C. And Hopper had also this feature but it was canceled/postponed (the fused dies solution was called GH202)

GH202 is not two H100 glued together.

 

[moinmoin]

Grace Hopper is like Infinity Fabric in that the interconnect is through substrate, no?

Infinity Fabric has nothing to do with an interconnect going through substrate. Infinity Fabric can technically go through anything or stay within the same die (as it does in APUs).

 

[HurleyBird]

From own AMD financial number, their CDNA sales is insignificant compared to A100 (not even 10%). So no, except the exascale government deals and one EU supercomputer, AMD GPUs have zero presence in HPC (yet). CDNA3 may change it tho

A100 and CDNA2 are different markets with some overlap. Former is all about AI (low precision flops) while the later is all about HPC (high precision tflops). Most A100 sales are not coming from HPC.

 

[xilli_fiberbit]

It could be some kind a refresh :

https://twitter.com/x/status/1563514947124207618

9 Chiplets navi3 started to be mass-produced. I was wondering what it was and why it was not a 7 but a 9. A navi with 13 Chiplets began development. It's still a long way from mass production, about a year from now.

 

[Mopetar]

It certainly is a possibility and may also explain some rumors that indicated a smaller than anticipated amount of infinity cache.

I'm curious if it will be something where they're trying to advertise 8K gaming capabilities, which would likely need a substantial increase in cache size so as not to bottleneck.

It may also benefit RT performance as that apparently requires some additional memory for the data structures that store that information and being able to keep more of that in cache might help AMD see some gains there as well.

 

[GodisanAtheist]

K so where the eff is the rumor mill now.

Navi 33 monolithic.

Navi 32/31 Chiplets with 7 total dies? (1+6)

Navi 32 with 9 Chiplets later? (1+8)

Navi 31 with 13 Chiplets later? (1+12)

God these card announcements cannot come soon enough.

 

[maddie]

That 9 chiplet being produced is the Skunk works, super secret, super GCD + 8 MCD product. Joking.

 

[Mopetar]

The other ones aren't really extra chiplets. I'm assuming they're just calling the v-cache die that gets stacked on the MCD an extra chiplet.

Whether they exist or not is another matter, but it makes a certain amount of sense as a mid-generation refresh part. Better than the usual 50 MHz boost bump that we've seen in the last.

 

[Saylick]

Allegedly AMD will do a "one more thing" and give a teaser for Radeon 7000.

https://twitter.com/x/status/1564376414018740225

 

[Karnak]

Hopefully more than just "this is X running on a RDNA3 GPU look how smooth it runs".

 

[RnR_au]

Usually there are enough data from a briefly glimpsed fps counter to satisfy the discussions for weeks

 

[jpiniero]

Allegedly AMD will do a "one more thing" and give a teaser for Radeon 7000.

You know, I was sort of expecting them to pimp RDNA 2 price cuts to try to encourage shifting inventory instead of talking about the 7000 series.

 

[Frenetic Pony]

That RNDA3 tease be like:

 

[moinmoin]

Hopefully more than just "this is X running on a RDNA3 GPU look how smooth it runs".

Spot on.

 

[Saylick]

lol. So RDNA 3 teaser is basically like Zen 4 teaser with the Halo demo. "It looks great, doesn't it?"

 

[RnR_au]

Not much of a tease. They showed the ankles. Not even a hint of a saucy knee aka fps counter

 

[Saylick]

Well, we know one thing for sure. Angstronomic's absolutely nailed it again:
"The reference card appears to have an updated 3-fan design that is slightly taller than the previous generation, with a distinctive 3 red stripe accent on a section of the heatsink fins near the dual 8-pin connectors."



What does that say about the rest of those leaks?

 

[desrever]

You know, I was sort of expecting them to pimp RDNA 2 price cuts to try to encourage shifting inventory instead of talking about the 7000 series.

AMD isn't sitting on massive inventories like Nvidia.

 

[jpiniero]

AMD isn't sitting on massive inventories like Nvidia.

Not as bad as nVidia but still seems bad. AMD started cutting prices way earlier and they have cut way deeper.

 

[GodisanAtheist]

Hopefully more than just "this is X running on a RDNA3 GPU look how smooth it runs".

-You've seen Doom '92 running on a tractor, an excell spreadsheet, even a pregnancy test. But have you ever seen Doom '92 running on AN RX7950 PEOPLE *crowd goes totally nuts, curtains close*

 

[Joe NYC]

One small thing that may have been a mistake / slip.

From SkyJuice, we are assuming there will be one 5nm chiplet and multiple 6nm chiplets.

I the presentation, they mentioned 5nm chiplets (plural)

 

[gdansk]

K so where the eff is the rumor mill now.

Navi 33 monolithic.

Navi 32/31 Chiplets with 7 total dies? (1+6)

Navi 32 with 9 Chiplets later? (1+8)

Navi 31 with 13 Chiplets later? (1+12)

God these card announcements cannot come soon enough.

isn't this 13 chiplet talk just the stacked cache? 1 gcd + 6 mcd + 6 stacked cache chips. Å says the stacked cache is optional, after all.

Can TSMC stack N5 on N6? I think that may mesh up

 

[Joe NYC]

isn't this 13 chiplet talk just the stacked cache? 1 gcd + 6 mcd + 6 stacked cache chips. Å says the stacked cache is optional, after all.

Can TSMC stack N5 on N6? I think that may mesh up

From various leaks, MCD should be on N6, and stacked cache should also be on N6.

But in general, both N5 and N7 should be eligible for both top and bottom die. But this picture may not be up to date.

In fact, TSMC should be updating its road map at some conference tomorrow.

 

[DisEnchantment]

Lel AMD devs leaking stuffs themselves inadvertently

Yellow carp's cache info cannot be duplicated to GC_11_0_1.

Different point to GC_11_0_1:
TCP L1 Cache size is 32
GL1 Data Cache size per SA is 256

Others looks good to me

--
Best Regards

[PATCH] drm/amdkfd: Match GC 11.0.1 cache info to yellow carp

Now I am wondering if the L0 and VGPR sizes are precise as mentioned by @Kepler_L2

https://twitter.com/x/status/1565627241937108992

 

[Kaluan]

So, any takers on if there will be a "together we advance_PCs part 2" centered around RDNA3 announcement/launch (and possibly Zen4+V-Cache as well, makes most sense TBH)?

Á la how they announced Ryzen 5000, followed by one (part 2) announcing RX 6000, ~2 years ago.

Edit: Maybe they drop another SAM/ReBAR bombshell this time too. Centered around vertical cache coherency (since both families will use it this gen)... or AI acceleration perks on RDNA3 uArch... idk I'm just spitballing nonsense at this point. But I suspect they will want to make another splash.