Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[Mopetar]

So with MCM the work distribution, what lanes run what, is all still centrally controlled. There's one input stream to deal with, and all the figuring out of how to get that instruction stream and results and those results back to where they're needed, back and forth across chiplets is done on the hardware itself. Over what needs to be a very high bandwidth, very low latency, preferably very cheap connection (thus why it's taken so long to make).

The problem with "sli" and whatever is indeed latency, in part, and bandwidth. And the fact that there's two instruction streams going to two different chips who then may have to shuttle data back and forth to each other, requiring a lot of bandwidth and consideration of latency (and complication, lots of it) over PCIE (which might be saturated at points already), or everything has to be copied out twice to both cards, meaning a lot of the benefit is lost as you can't perfectly "split the screen in half" and have one card to one half and the other do the other half.Either way, you can pay double the cost for something that is not double the performance.

Meanwhile if you split a GPU in two each half costs less than one big whole, depending on the sizes as splitting a 200mm chip into 2 100mm chips you don't save much and it might even cost more as you end up needing extra hardware for that link between chiplets. But if you split a big enough chip, like a huge GPU or a 64 core CPU or etc. into two or more chiplets then even with some extra added hardware and etc. for chiplet cost your overall cost goes down.

Outside of latency (and I suppose multiple PCI bus connections) though what is the difference between coordinating two chiplets in the same PCB or two chiplets on different cards?

What would prevent the same issues with SLI/Xfire implementations from occurring or not needing the additional work from developers to extract the performance gain.

From the past we know that it's possible to get 70% plus scaling with SLI/Xfire and in some cases it's about as close to perfect as could be expected. In those cases not even the inter-card latency matters more than a percentage or two in terms of raw performance.

Presumably for AMD to have an MCM approach means that some part of the issue that prevents SLI/Xfire from just working without additional support from developers has been solved.

 

[maddie]

Outside of latency (and I suppose multiple PCI bus connections) though what is the difference between coordinating two chiplets in the same PCB or two chiplets on different cards?

What would prevent the same issues with SLI/Xfire implementations from occurring or not needing the additional work from developers to extract the performance gain.

From the past we know that it's possible to get 70% plus scaling with SLI/Xfire and in some cases it's about as close to perfect as could be expected. In those cases not even the inter-card latency matters more than a percentage or two in terms of raw performance.

Presumably for AMD to have an MCM approach means that some part of the issue that prevents SLI/Xfire from just working without additional support from developers has been solved.

I don't understand the assumption that chiplet = complete stand alone GPU.

 

[GodisanAtheist]

I don't understand the assumption that chiplet = complete stand alone GPU.

...and from the sound of the rumors, we're not even getting multiple logic chiplets. Sounds like cache/memory controller/Io chiplets etc which are a completely different beast than logic dies.

People are really making some wild and crazy assumptions based on a couple extre *pci-e* ports...

 

[Mopetar]

...and from the sound of the rumors, we're not even getting multiple logic chiplets. Sounds like cache/memory controller/Io chiplets etc which are a completely different beast than logic dies.

People are really making some wild and crazy assumptions based on a couple extre *pci-e* ports...

The rumors seem to have changed at some point, but once upon a time it seemed like there were multiple dies that contained the shaders. They certainly could have a design that has all of the compute on a monolithic die that connects to multiple cache dies that also handle the memory interference connections.

Perhaps the lack of multiple shader chiplets does indicate they haven't worked out all of the problems there yet.

 

[eek2121]

The rumors seem to have changed at some point, but once upon a time it seemed like there were multiple dies that contained the shaders. They certainly could have a design that has all of the compute on a monolithic die that connects to multiple cache dies that also handle the memory interference connections.

Perhaps the lack of multiple shader chiplets does indicate they haven't worked out all of the problems there yet.

I suspect the problem is more logistical than anything else. Moving to one chiplet means they can make twice as many cards, and they probably realized that raising clocks allows them to hit internal performance targets just as easily.

 

[Frenetic Pony]

I suspect the problem is more logistical than anything else. Moving to one chiplet means they can make twice as many cards, and they probably realized that raising clocks allows them to hit internal performance targets just as easily.

There's a number of advantages to one IO chiplet and one compute. 6nm should be more available and, probably, cheaper to produce (it's definitely cheaper to design) than 5nm, and since it doesn't take up as much power relative to compute that's not as much of a priority, nor does it need ultra high clockspeeds.

The odd part of needing to grab everything from ram and then shuttle it across to the compute chiplets, increasing power cost and complication there, might still be worth things like cost savings. On top of that you get the idea of tik/tok cycle of upgrading your IO and compute chiplets separately. Chip design costs a hell of a lot these days in both money and time, and getting out upgrades regularly is helpful for staying up with the competition.

But there are arguments against it. Moving to newer node like 5nm would save power on IO regardless, both from improved power usage when retrieving stuff and from less need to shuttle traffic across chiplets. It also means you can just, potentially design one chiplet and then put as many of those as you need on package, incredibly easy scalability! So it's all a bunch of tradeoffs.

 

[Dribble]

I suspect the problem is more logistical than anything else. Moving to one chiplet means they can make twice as many cards, and they probably realized that raising clocks allows them to hit internal performance targets just as easily.

There seems to be some assumption that moving to chiplets is easy, but it's not. You introduce a load of problems with the sharing of resources and how to break up execution between the chiplets, particuarly for games where the whole lot needs to generate a single output (a frame). Almost certainly the reason AMD haven't done it is they haven't got it working seamlessly or efficiently yet.

 

[GodisanAtheist]

There seems to be some assumption that moving to chiplets is easy, but it's not. You introduce a load of problems with the sharing of resources and how to break up execution between the chiplets, particuarly for games where the whole lot needs to generate a single output (a frame). Almost certainly the reason AMD haven't done it is they haven't got it working seamlessly or efficiently yet.

"If it was easy someone would have done it already"

 

[biostud]

There seems to be some assumption that moving to chiplets is easy, but it's not. You introduce a load of problems with the sharing of resources and how to break up execution between the chiplets, particuarly for games where the whole lot needs to generate a single output (a frame). Almost certainly the reason AMD haven't done it is they haven't got it working seamlessly or efficiently yet.

Not being an expert in any way, but in the end isn't about latency between the different chiplets? Even in a single GPU you have to data around from the thousands of cores inside a modern GPU.

 

[eek2121]

There seems to be some assumption that moving to chiplets is easy, but it's not. You introduce a load of problems with the sharing of resources and how to break up execution between the chiplets, particuarly for games where the whole lot needs to generate a single output (a frame). Almost certainly the reason AMD haven't done it is they haven't got it working seamlessly or efficiently yet.

Oh I never said it was easy. However AMD has filed many patents, and they have had plenty of time to get it right. The fact that the “leaks” changed so late in the game suggest either a last minute problem or a logistical issue. Normally you would think there was a problem, however, it wasn’t long ago that GPUs were very hard to find. AMD may wish to avoid a repeat of that.

EDIT: and with their Ryzen chips hitting 5.5ghz, chances are good that their GPUs will see a large clockspeed increase as well.

 

[Aapje]

The leaks can also change late in the game because they are just guesses and not actual leaks.

 

[eek2121]

The leaks can also change late in the game because they are just guesses and not actual leaks.

The leaks came from credible sources, so they are more than just “guesses”

 

[uzzi38]

The leaks came from credible sources, so they are more than just “guesses”

Not credible enough ones, apparently.

 

[ModEl4]

Can someone summarize what is the current "consensus" for N31 vs N21 regarding gaming performance jump based on the unofficial AMD leakers?
Before one year or around that time we had 2.5X-3X depending the leaker (specifically mentioning gaming performance (not FP32) difference...)

 

[uclaLabrat]

I feelnlike its still hovering around 2-2.5x based on leaked specs but its all hand waving.

 

[ModEl4]

I feelnlike its still hovering around 2-2.5x based on leaked specs but its all hand waving.

Thanks, is this 2-2.5X from the same known leakers, or is it your interpretation based on the specs and leaks?
I have my own prediction, I just wanted to see how far is it from the current official-unofficial leaks and if they changed tune.

 

[Aapje]

My estimate would be 1.5 to 2 times across the line up for rasterization and more than that for ray-tracing.

I think that the higher estimates that leakers give are for ray-tracing.

 

[jpiniero]

My estimate would be 1.5 to 2 times across the line up for rasterization and more than that for ray-tracing.

That isn't going to be enough versus nVidia's top models. Now I could see AMD seeing the TSMC price increases and mining slump and getting scared that they don't have the ability to sell $2k+ cards regardless of competitiveness. Esp if N31 is going to be released 6 months later.

 

[Saylick]

Seeing as how N33 is supposed to beat the 6900XT at 1080p, match it at 1440p, and lose to it at 4K, I think 2x 6900XT is conservative for N31, which is in essence triple N33 in specs (3x the shaders, 3x Infinity Cache, allegedly 3x the memory bus width). The only thing that isn't 3x is the TDP, which is closer to 2x, maybe 2.5x tops (assuming N33 is 200W, N31 is 450W). How high it can scale is anyone's guess, but 2x seems like a good floor. Personally, I'd like to see 2.5x 6900XT, which puts it at roughly 2.2x RTX 3090. They kind of need it that fast if they want to compete at the super high end.

 

[Aapje]

That isn't going to be enough versus nVidia's top models.

That assumes the gains at the top end are real and not just due to extreme overclocking, which AMD can just copy.

 

[jpiniero]

That assumes the gains at the top end are real and not just due to extreme overclocking

It's both. Remember it's basically a double shrink. Maybe even more than that when you factor in how garbage quality wise SS8 is.

 

[maddie]

It's both. Remember it's basically a double shrink. Maybe even more than that when you factor in how garbage quality wise SS8 is.

At a high level, processing throughput efficiency, shader numbers & speed are what matters. SS8 vs N4 is merely one of the building blocks to achieve the end result. Using the node as you do here is deceptive.

 

[jpiniero]

At a high level, processing throughput efficiency, shader numbers & speed are what matters.

And it has that. AD102 has 70% more SMs. Clocks should be a lot higher.

 

[maddie]

And it has that. AD102 has 70% more SMs. Clocks should be a lot higher.

Yes, so why SS8 in the post? The final output parameters are what's important.

 

[jpiniero]

Yes, so why SS8 in the post? The final output parameters are what's important.

SS8 definitely limited the performance of Ampere. Power consumption worse, etc.