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Question Speculation: RDNA3 + CDNA2 Architectures Thread

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VCN 4 getting prepped for landing in the next merge window.

AV1 encode seems not supported?

C: 
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =
{
    {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
    {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
};


Previous commit indicate that up to 4x VCN instances can be present.
 
DisEnchantment said:
VCN 4 getting prepped for landing in the next merge window.

AV1 encode seems not supported?

C: 
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =
{
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
};


Previous commit indicate that up to 4x VCN instances can be present.
Click to expand...
Lets not get ahead of ourselves on what codecs are and aren't supported, lest we get another Rembrandt situation again.
 
Glo. said:
To be honest, me too.

I know that 3 GHz is conservative. The question remains: what exactly is AMD capable of achieving with the 5 nm process and their physical design team.

If its 92 TFLOPs, and if its 12280 ALUs - its 3.7 GHz clock speed.
Click to expand...

That is a shame.

A 7970XT 3Ghz edition just has a nice nostalgic ring to it. 3.3Ghz edition does not quite hit the spot.

To be honest though anything around or north of 3Ghz is pretty mind blowing for a GPU at a moderate TBP.
 
Glo. said:
If its 92 TFLOPs, and if its 12280 ALUs - its 3.7 GHz clock speed.
Click to expand...
92 TFLOPS is an outdated figure that Greymon computed based on his previous, higher (60 WGP) expectations. He said so himself, that is irrelevant now. No way it hits 92 TFLOPS at stock.
 
TFLOPS doesn't even matter, to be honest. Performance and fps is where the money is at. It could be 69.69 TFLOPs but if it performed like 2.69x 6900 XT at 4K , no one would complain that the TFLOP number was suspect.
 
Ahh, found it: https://wccftech.com/amd-next-gener...navi-3132-and-33-updated-gpu-variants-leaked/

That they keep changing these numbers up gives reason to be skeptical of all these "leaks". That being said I could easily see the supposed N33 not being a "separate" card at all, but just one main chiplet instead of two as the numbers between N33 and N32 match up perfectly for that.

Edit- Ideally of course that "big" one would just be, get this, 3 main GPU chiplets! (n33 x 3) Design once, use everywhere. 192bit bus to 576bit bus, the higher you go for losing chiplets due to defective placement the higher the margins so who cares. One chip for your entire lineup, with one SRAM chip design possible as well. Just space them 96/192/288mb of sram on top. Last one should be enough to hit 8k in certain games, middle one enough for good 4k, low one perfect for 1440p.

At the very least now the leaks are starting to sound more reasonable. That lowest N33 one could easily sell for $400 and be close to a 6800xt. Probably sell as many as they could build if that were the case.
 
Last edited:
uzzi38 said:
Don't expect 3.7GHz stock. Maybe overclocked, but not stock.
Click to expand...

If f 3.7 GHz is possible it won't be on the big cards. RDNA 2 could already get close to 3 GHz, just not with Navi 21. Meanwhile the smaller Navi 24 has a 2.8 GHz boost out of the box. For all I know someone has OC'd it to 3 GHz already.
 
Frenetic Pony said:
At the very least now the leaks are starting to sound more reasonable. That lowest N33 one could easily sell for $400 and be close to a 6800xt. Probably sell as many as they could build if that were the case.
Click to expand...

I still insist that both N33 will be more than the 6750 XT's MSRP. Maybe if they keep the size down it won't be that much more.

Mopetar said:
Any summary of the video for those of us who can't watch it right now?
Click to expand...

Youtubers gonna Youtube. Just some claims of well over 3 Ghz.
 
Mopetar said:
Any summary of the video for those of us who can't watch it right now?
Click to expand...
Navi 31 consists of 1 GCD. Yes, SINGLE GCD with 12280 ALUs. Two possibilities for memory bus width: 384 or 256 bit bus. 384 MB IC.

All 48 WGPs on a SINGLE GCD, according to his latest information. Let this sink in.

Performance targets for SINGLE GCD - the same, according to his latest information: 2.5 times the performance of 6900 XT.

I don't even know what to say. Yes, it looks ridiculous. But his type of rumor mill we have just experienced with RDNA2 GPUs. And at the end, it all turned out to be true.
 
Why 1 GCD and not 1.5? You cut one GCD in half, by cutting each transistor exactly in half.

The above is a total bullshit, like most of these "leaks".
 
I needed to rewatch whole video to make sure that I heard it correctly, what Paul is saying, andf yeah, it appears that is what he says.

Its hard to believe it to be possible.

On the other hand, its just 20% more WGPs on a single die, compared to Navi 21: N21 had 40 WGPs. N31 supposedly has 48 WGPs.
 
Just watching it now and trying to summarize his ramblings... (dude seriously needs to storyboard his videos instead of phoning them in each time).

First set of specs:
1651604874222.png

He says RT uplift for N31 is 4x over N21.

1651604888764.png

He says N33 clocks are "well north of 3 GHz".


For the second set of specs, it's what @Glo. is trying to convey but I am not convinced it is legit since he says it is NOT 3D stacked.

1651605209953.png


Some rumors for Phoenix... take with a grain of salt:
1651605263038.png
 
Glo. said:
I needed to rewatch whole video to make sure that I heard it correctly, what Paul is saying, andf yeah, it appears that is what he says.

Its hard to believe it to be possible.

On the other hand, its just 20% more WGPs on a single die, compared to Navi 21: N21 had 40 WGPs. N31 supposedly has 48 WGPs.
Click to expand...
Except gfx11 WGP have twice the SIMDs, twice the cache, etc. It's not feasible on 5nm.
 
With Infinity Cache in RDNA2 AMD seemed to prepare RDNA for an MCM design, decoupling the need for shared high bandwidth connections to memory. To then make the biggest RDNA3 model use a single huge die instead using MCM for outrageous scaling like successfully with Zen CPUs makes zero sense in that context.
 
moinmoin said:
With Infinity Cache in RDNA2 AMD seemed to prepare RDNA for an MCM design, decoupling the need for shared high bandwidth connections to memory. To then make the biggest RDNA3 model use a single huge die instead using MCM for outrageous scaling like successfully with Zen CPUs makes zero sense in that context.
Click to expand...
Yep, which is why I presonally very much doubt the "second" specs of N31.
 
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