- Sep 23, 2011
It's a follow up of the patent "super-simd", RDNA3 can (aparently) chain mutiple instructions in theyr dual ALUs, pretty much bouncing the results of one alu to another... it's nothing alike the old gpusCan the smarty pants in this thread break down this VLIW news a bit? I recall AMD was on VLIW5/4 with with their og Dx10/11 archs, but moved away from VLIW for GCN and up because of occupancy issues and the arch's weakness with compute workloads etc.
What does VLIW"2" do for AMD in modern workloads and how does it overcome the issues that got AMD to move away from it in the first place?
This last patent descibes that a compiler keeps track of any dependencys, and if it finds one, it can delay one ALU while it waits for the results of another... Aka, it makes the gpu lose 1 or 2 cicles to avoid a complete gpu stall