https://lists.freedesktop.org/archives/amd-gfx/attachments/20200727/dfe69333/attachment-0001.obj
Seems like Sienna (at least some variant of it) will have ECC and possibly HBM (2048 bit interface)
Seems like Navy Flounder does not have it.
GMC10 updated to handle this ECC/RAS update.
UMC 6.1 is for Arcturus.
UMC 8.7 is for Sienna.
UMC
C++:
+/* HBM Memory Channel Width */
+#define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH 128
+/* number of umc channel instance with memory map register access */
+#define UMC_V8_7_CHANNEL_INSTANCE_NUM 2
+/* number of umc instance with memory map register access */
+#define UMC_V8_7_UMC_INSTANCE_NUM 8
+/* total channel instances in one umc block */
+#define UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA 0x400
UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM) = 16.
Bus width = Num channels * Channel Width = 16*128 = 2048
GMC
C++:
+static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
+ adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+ adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
+ adev->umc.funcs = &umc_v8_7_funcs;
+ break;
+ default:
+ break;
+ }
+}
There are some final bits missing to confirm this, but it seems like 2048 bit HBM will be present for Sienna (at least some variants)
Eventually the bus width is read from atombios, but 2048 would be the max. (2048 bit Flashbolt would give 819 GB/s or if Hynix HBM2e would be an astounding 921 GB/s, but if anything it would probably downclocked versions of these)
In comparson, for Arcturus
C++:
/* HBM Memory Channel Width */
#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128
/* number of umc channel instance with memory map register access */
#define UMC_V6_1_CHANNEL_INSTANCE_NUM 4
/* number of umc instance with memory map register access */
#define UMC_V6_1_UMC_INSTANCE_NUM 8
/* total channel instances in one umc block */
#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
/* UMC regiser per channel offset */
#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20 0x800
#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT 0x400
Bus width = 4096 (4*8*128).
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