Well... I have lots of time and I thought I might take a stab at this (measuring few blobs and pixelated die shots.)
I measured the various blocks for Navi 10 using the annotated die shots from Fritz and using ImageJ to measure the area to correlate and get the size of the blocks.
View attachment 20419
It turns out that total CU size for Navi10 is only 1/3 of its total die size and that a single CU (1/2 WGP) is quite small only ~2 mm2
So to speculate on the size for Big Navi... using Navi10 dimensions.
1.5x Memory+PHY (384Bit), 1x IO,
2x RBE(128ROPs),
4x L1,
2x ACE/HWS,
4x L2,
3x Raster/Primitive Unit and
2.5x WGP(100CUs) comes to about 500mm2. Keeping IO same, added 128bit more channel, doubled the ROP, L1, L2. Tripled the Raster
From Microsoft XSX die picture (which I have manipulated the perspective with GIMP), we take out the Zen2 Core, the PHYs etc, we have 175-185mm2 for the GPU cores if measured the same way as above.
ASSUMING 65% of the GPU core part (outside of IO and PHYs) is for the CUs (using the ratio of Navi 10) we have around
~2.2 mm2 for each CU. This could be because it seems XSX is fairly space efficient even when the HW RT is inside the CU.
So based on this, I could speculate that if the die size of 505 +/- 5% is correct,
1.5x Memory+PHY (384Bit), 1x IO,
2x RBE(128ROPs),
4x L1,
2x ACE/HWS,
4x L2,
3x Raster/Primitive Unit and
2.5x WGP(100CUs) comes to about 505mm2.
~100 CUs could indeed be possible, with double the ROPs, 384 Bit GDDR and so on.
And that is 25 mins of of excel math and GIMP/ImageJ skills put to speculation use.
Block measurements from ImageJ and Perspective changed image with GIMP