Some Sandy Bridge details

imported_Shaq

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Sep 24, 2004
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"According to the noises heard in corridors at a manufacturer of motherboard, the CPU should resume Socket 1156 of Clarkdale (generation "Westmere" above) but require a new chipset."

Interesting. Too bad it won't work with soon to be current 1156 motherboards. This is the mainstream version of Sandy Bridge that is discussed in the article so the 8 core version may require a motherboard with more pins.
 

ilkhan

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Jul 21, 2006
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I expect the 8 core will require s1366 and be without onboard GPU. Basically the same split as current, more cores and multi socket vs more integration and cheaper.
 

KingstonU

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Dec 26, 2006
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Is this supposed to be Larrabee? That's all I think about when I read how the GPU is on-die with the CPU package. Too bad AMD's Fusion got delayed so much, it was supposed to be out this year originally but now I think they've been saying it will be 2011 or later.
 

ilkhan

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Jul 21, 2006
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no, sandy won't have larrabee based iGPU. But it will be the first on die GPU, and the first at 32nm.
And is it just me or does having an actual chip 15 months before launch seem really early?
 

Keysplayr

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Jan 16, 2003
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Does seem like a long time. Doesn't this still have to go through Intels qualification process? If so, how long does that generally take if all goes well?
 

ilkhan

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Oh, this is very early silicon, almost certainly the among the first dies to come out. May or may not be working, etc. But it seems the initial design is done, taped out, applied to silicon, and being refined.
 

PlasmaBomb

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Nov 19, 2004
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Originally posted by: ilkhan
Oh, this is very early silicon, almost certainly the among the first dies to come out. May or may not be working, etc. But it seems the initial design is done, taped out, applied to silicon, and being refined.

Yup it is A0 silicon, expect a few respins before they iron out any problems.
 

ilkhan

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Jul 21, 2006
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A0, thats the term I was searching for.
yeah. Is it normal for A0 silicon to be out 15 months prior to release?
OT edit: as somebody that can edit a post 5-6 times before being satisfied with it, the lack a a 2-3 minute ninja edit window annoys me. :( I guess thats what preview is for.
 

Idontcare

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Oct 10, 1999
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Originally posted by: ilkhan
Is it normal for A0 silicon to be out 15 months prior to release?

Yes it is, for IC's of this complexity it is actually a bit fast. I've seen 65nm designs (much much less complex than 32nm) take 24months from tapeout/A0 to production/commercial release.

The verification cycle can be a real bitch, tukwilla and rock anyone?
 

IntelUser2000

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Oct 14, 2003
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Originally posted by: Idontcare
Originally posted by: ilkhan
Is it normal for A0 silicon to be out 15 months prior to release?

Yes it is, for IC's of this complexity it is actually a bit fast. I've seen 65nm designs (much much less complex than 32nm) take 24months from tapeout/A0 to production/commercial release.

The verification cycle can be a real bitch, tukwilla and rock anyone?

Isn't it usually 9-12 months for Tapeout to mass production?? Considering that, a June tapeout for a Q1 release seems pretty early. It probably has to do with Intel wanting to phase out Westmere before Sandy Bridge, but the right now the silicon is sure healthy.
 

ilkhan

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Jul 21, 2006
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CPU talking! And to get back into the bath, here is a small summary of the news coming from Intel in the coming months. Currently, the latest generation of processors available - those of the Core i7 - is based on the architecture "Nehalem", which has gradually replace the Core 2. The Quad-Core CPUs based on Nehalem are currently recorded in 45 nm and from September will be made in "Core i5, much more economical. In the second quarter 2010 (Q2'10) will appear first processors' Westmere ', always based on the Nehalem architecture. These will be the first recorded in 32 nm and some of them incorporate a chip integrated graphics (IGP) in the form of a second chip integrated on the same packaging. It was not until 2011 that Intel expected to announce its new architecture, named "Sandy Bridge".

In the labs of Intel, it is already on all future CPU. To learn more, we left our ears trainer over to reveal the current status of these projects. Core i5 'Lynnfield' are already packaged in their final boxes and will soon be ready to be delivered in mass among wholesalers. The first prototypes of processors based on 32 nm Westmere are themselves out of the factories (Tape-Out) at the beginning of the year and work very well in the regional R & D. The first of them, "Gulftown", a 6-core processor "Extreme Edition" equipped with 12 MB L3 cache will be available around May 2010 and was announced as being compatible with the motherboards X58/LGA1366 current.

But the most interesting is probably the Tape-Out early in June the first CPU to generation "Sandy Bridge", the next Intel microarchitecture. In hallucinatory world exclusive worldwide PC Canard unveils first photo of the newborn, barely a month. The A0 stepping die in this time is that of a processor Mainstream, ie designed to be integrated in a very large number of machines as sold at a reasonable price. It features quad-core, Hyper-Threading, the AES instructions of its predecessor, but also the famous new calculation unit vector "AVX", which leverages the capabilities of the SSE units as they previously knew. This time, it is now possible to use 4-bit operands of 256 instead of 2 / 3 operand 128 bit with the latest versions of SSE. Every heart of Sandy Bridge is equipped with 256 KB of L2 cache and shared L3 cache of 8 MB to which access has been accelerated through a ring architecture (ring). Time-to-L3 cache and fall to a minimum of 25 cycles. But that's not all: Sandy Bridge includes a Northbridge-based PCI Express links (over QPI in the Mainstream) and a dual memory controller supporting DDR3-1600.

Another innovation is the integrated GPU (IGP) that is both incorporated within the processor and therefore also recorded in 32 nm. Thanks to this reduction, access to L3 cache (which can also use it) and fast memory controller, the performance of this IGP should be comparable to those graphics cards input range of ATI and Nvidia in 2011. The size of this declination Quad Core Sandy Bridge is approximately 225 mm ² (each heart measuring about 20 mm ²) for a heat dissipation of about 85 Watts. Frequency side, it will take some steppings to know the limits of the heart, but initial estimates are between 2.8 and 3.4 GHz, with a Turbo mode between 3.8 and 4 GHz. Remember, this processor will not be the high end of the day. Other versions with 2 and 8 hearts are also provided (with respectively 4 and 16 MB L3 cache), but are not yet available at the prototype stage.

While we can not reveal to you some details of the architecture in the heart of Sandy Bridge, a few remain unknown. First, the Socket. According to the noises heard in corridors at a manufacturer of motherboard, the CPU should resume Socket 1156 of Clarkdale (generation "Westmere" above) but require a new chipset. Then, the performance of the integrated circuit graphics are all subject to speculation. We already know that the IGP Sandy Bridge will always be based on GMA and not on any variation of Larabee. With a frequency of approximately 1.2 GHz, this heart intended to be compatible with DirectX 11, should not be ridiculous but be a lightning war. Finally, the number of PCI Express link is still unknown. According to the first draft of the datasheet, this heart contain 20 lines PCI Express 2.0 (16x + 4x), but the information could not be confirmed ...
The translated text. :)

http://yfrog.com/0jsnb24960353665671878j
The die shot

And July 09->Nov '10 is 18 months. So that sounds more accurate.
 

Idontcare

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Oct 10, 1999
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Originally posted by: ilkhan
I expect you are tired of my posts by now, but I made a chart. Its mostly for cache latency. Looks to be quite improved.
http://img27.imageshack.us/img27/8203/captureuef.jpg

I like the table, care to add westmere to it so we can easily see whether the reduced latency caches are shared between the two architectures?

Originally posted by: ilkhan
The translated text. :)

Thank you very much for that :beer:

Originally posted by: IntelUser2000
Isn't it usually 9-12 months for Tapeout to mass production??

It can be that quick, and even quicker in some cases, but to say "usually" for anything relating to tapeout to volume production timelines you need some way to normalize the data as IC complexity and project resources obviously dictate 98% of the actual timeline.

For GPU's, arguable of similar verification complexity in some cases, the timeline can be as short as 4-6 months if the resources are willing.

But I don't find 15months to be beyond the +/- 1-sigma portion of the distribution centered on the mean (say 12 months) for the expectation of most projects in this day and age.
 

ilkhan

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Jul 21, 2006
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Its wierd, I don't think Ive seen that kind of data on westmere. I'll update it if you can find me some data. :)
 

IntelUser2000

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Oct 14, 2003
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I like the table, care to add westmere to it so we can easily see whether the reduced latency caches are shared between the two architectures?

There are no figures, but since the article explicitly states the reason for dramatically reduced L3 latency is due to the Ring Bus, that probably won't be changed.

I can see the 3 cycle L1 cache being possible though. It might have been process limited on 45nm.

On something little different than what we are currently going to. I think the 1-1.4GHz estimated clock on the integrated GPU means something. That may be graphics Turbo Mode.

Okay, if the graphics are really DX11, the pure performance of the GPU needs to be significantly higher than current generation. DirectX 10.1 has a 4xAA mandatory requirement and at the moment, Intel's X4500 doesn't even have AA! Although I believe the BIG performance jump is going to come in the Nehalem generation, aka Clarkdale...

To Idontcare: 50mm2 for a GPU is not big at all. The G965 had 70% of its 120mm2 die as the GPU portion. Clardale's MCM GMCH portion is around ~135mm2. Which is a LOT of extra transistors considering G45 that's on 65nm has a die size of only 98mm2.