Some Bulldozer and Bobcat articles have sprung up

[Janooo]

Just to give a very rough idea, without L3 cache, a single core PII with IMC/NB and Hyper Transport links would account to ~58% of the die size, and around ~42% for 2MB L2 cache area.

Adding a second core to the above mentioned configuration (without adding more L2 cache) would only drop the 2MB L2 die area to ~30%, and ~70% would be for the dual cores and everything else.

BTW, it's useless to try to apply these numbers to BD, because BD is a completely new architecture on a 32nm process, I got my rough calculation from an Athlon II X2 die shot.

What picture did you use?

 

[Martimus]

It looks like the Ontario chip has a TDP of 9W (http://vr-zone.com/articles/amd-ontario-tdp-is-9w-die-shots-revealed/9754.html)

Also included in that article is a picture of the die.

Zacate (which I didn't hear about until just now to be honest) has a TDP of 18w, and is a higher clocked version of the Bobcat, meant to be used in laptops. This version will actually be available at retail according to the article. (The Ontario chips are BGA and will not be available at retail, only as part of a system)

EDIT: I didn't mention this since it was already mentioned in the video forum, but the shipping date has moved from Q1 2011 to Q4 2010.

 

[Kuzi]

What picture did you use?

I used the pic from Anand's review below:

http://www.anandtech.com/show/2775

I got a better idea about the cache dimensions from Hans De Vries pics, you can find a Shanghai/Deneb pic in a thread below:

http://aceshardware.freeforums.org/finally-an-image-of-shanghai-t405-15.html

Notice how according to Hans, 1MB L2 cache on K10 takes about 7.5mm^2, so 2MB require about 15mm^2. A single core K10 takes about 15mm^2, that takes the core+L2 cache to over 30mm^2 in size. The uncore part is the rest (I calculated your CPU at ~70mm^2).

Actually I made a mistake the first time, and calculated 4MB L2 instead to 2MB. And the total die size should be closer to 66mm^2, so a more accurate die size representation would be:

~23% die size for 2MB L2 cache, and ~77% for the rest.