Socket 1207 Intro

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Pederv

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May 13, 2000
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What's stopping AMD from slapping a couple low power opterons together in a 1207 package and anouncing availability of quad core when the socket F platform launches?
 
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Griswold

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Dec 24, 2004
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Originally posted by: Soviet
Lousy marketing team.
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Maybe if you explain to them how this is related to marketing (in the server segment, mind you), they could learn a thing or two from you. Not saying AMD has brilliant PR monkeys on their payroll, but certain things dont make sense... ;)
 
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Griswold

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Dec 24, 2004
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Originally posted by: coldpower27
There are no roadmaps for Quad Core this year.
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Doesnt mean much when talking about AMD. Their roadmap policy is questionable at best.
 
Hard Ball

Hard Ball

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Jul 3, 2005
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Originally posted by: Pederv
What's stopping AMD from slapping a couple low power opterons together in a 1207 package and anouncing availability of quad core when the socket F platform launches?
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Extra latency to access memory, from two the the cores. Since the MCM package would basically include to cross-bars, there would be the need for some type of HTT protocol communication between those two dice. And in order for the second pair of cores to access memory, an extra hop over HTT link would be needed, since only one dual channel mem controller exists for S1207 chips.

It would give them bragging right, but makes about as much sense as Clovertown and Kentsfield.
 
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Pederv

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May 13, 2000
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Haven't been able to find a working pinout of socket F, so I always assumed that some of those 250+ extra pins were going towards a second memory channel, to maintain memory bandwidth when quad core became available.
 
Hard Ball

Hard Ball

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Jul 3, 2005
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Originally posted by: Pederv
Haven't been able to find a working pinout of socket F, so I always assumed that some of those 250+ extra pins were going towards a second memory channel, to maintain memory bandwidth when quad core became available.
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Always keep in mind that: if that were really the case for S1207's future, there would need to be 4 matching DIMMs for each socket for optimum performance. I don't really think that's the route AMD would want to go.

The extra pins are much more likely to be required because of future compatibility with DDR3, FBDIMM, future power requirements, and perhaps future further integration of NB functions on die (such as PCIE).

 
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