• We’re currently investigating an issue related to the forum theme and styling that is impacting page layout and visual formatting. The problem has been identified, and we are actively working on a resolution. There is no impact to user data or functionality, this is strictly a front-end display issue. We’ll post an update once the fix has been deployed. Thanks for your patience while we get this sorted.

Socket 1207 Intro

P

Pederv

Golden Member
What's stopping AMD from slapping a couple low power opterons together in a 1207 package and anouncing availability of quad core when the socket F platform launches?
 
Originally posted by: Soviet
Lousy marketing team.
Click to expand...

Maybe if you explain to them how this is related to marketing (in the server segment, mind you), they could learn a thing or two from you. Not saying AMD has brilliant PR monkeys on their payroll, but certain things dont make sense... 😉
 
Originally posted by: Pederv
What's stopping AMD from slapping a couple low power opterons together in a 1207 package and anouncing availability of quad core when the socket F platform launches?
Click to expand...


Extra latency to access memory, from two the the cores. Since the MCM package would basically include to cross-bars, there would be the need for some type of HTT protocol communication between those two dice. And in order for the second pair of cores to access memory, an extra hop over HTT link would be needed, since only one dual channel mem controller exists for S1207 chips.

It would give them bragging right, but makes about as much sense as Clovertown and Kentsfield.
 
Haven't been able to find a working pinout of socket F, so I always assumed that some of those 250+ extra pins were going towards a second memory channel, to maintain memory bandwidth when quad core became available.
 
Originally posted by: Pederv
Haven't been able to find a working pinout of socket F, so I always assumed that some of those 250+ extra pins were going towards a second memory channel, to maintain memory bandwidth when quad core became available.
Click to expand...

Always keep in mind that: if that were really the case for S1207's future, there would need to be 4 matching DIMMs for each socket for optimum performance. I don't really think that's the route AMD would want to go.

The extra pins are much more likely to be required because of future compatibility with DDR3, FBDIMM, future power requirements, and perhaps future further integration of NB functions on die (such as PCIE).

 
You must log in or register to reply here.

TRENDING THREADS

Back
Top