It seems that when rambus is placed in pairs on the i850 its pretty kickass. I have been reading that when the RDRam Dimms are placed in pairs on the i850 latency is effectively reduced because of the 32bit data pathway that is created. My question is if you have all 4 slots full would the pathway become 64 bit thus increasing performance even more? or would that require each memory bank to have 4 slots rather than 2.
So Rambus isnt as bad as we thought..
- Thread starter Cknyc
- Start date
Adul
Elite Member
it is 32 bits because it is a dual channel solution. If you want 64 bit pathway, then you would need a 4 channel solution. Which would require 4 Rimms for it to work.
yeah, from what thier saying rambus has huge potential, so i'll keep my eyes on it, but for now my next upgrade will be an amd ddr system, so I'll keep my eyes on intel and rambus, and maybe if they get rambus tweaked, I'll have a good reason to go back. . . . in a few years
Where have I been? It is possible to have 4 CHANNEL memory traffic on the i850? 16x4=64bit data path? 3.2 gb/s bandwidth? or would that be 6.4 gb/s bandwidth? I don't think you can have 4 channels only 2?
Would a 4 slot solution be difficult to manufacture? It would be great to drop 4 64 or 128mb dimms in that sucka and at the same time add another processor. Only problem is that it sounds expensive. I agree Ark Aoss, my next machine will be a 760mp w/ddr.
Fkloster, I w as going to name the thread "Was Fkloster right all this time?" Then start it off suggesting you are probably sitting at your desk laughing at all us A$$holes for doubting you..
I don't know, but I thought Rambus sucks because:
Overpriced
They want to make money with lawyers, not with products
RDRAM isn't _much_ faster than normal PC133 SDRAM, but it is faster
am I right?
Overpriced
They want to make money with lawyers, not with products
RDRAM isn't _much_ faster than normal PC133 SDRAM, but it is faster
am I right?
I agree, but the reason they first started to suck is because Intels i820 solution was suck and RDRAM was $1000 for 256M. The i850 is less suck than the i820,840. Then down the road Rambus itself became more is suck because of their litigations. Almost forgot Rambust is still relatively expensive compared to SDRAM but hopefully prices will decline someday.
I hope my rendition of the Rambus history is correct. I also hope I used "is suck" correctly..
I hope my rendition of the Rambus history is correct. I also hope I used "is suck" correctly..
PC-800 on a i820 (single channel: Ouch 
thats my rig...) setup is not much if @ all faster than an equally equipped PC-133 setup because the chipset cannot take advantage of the bandwidth. i850 (& i840 for that matter) have dual channel capabilities effectively doubling the datapath & bandwidth of PC-800. So far though the benchmarks are not showing that real world apps are taking advantage of anything that says "Rambus" on it... yet. (or maybe never)
thats my rig...) setup is not much if @ all faster than an equally equipped PC-133 setup because the chipset cannot take advantage of the bandwidth. i850 (& i840 for that matter) have dual channel capabilities effectively doubling the datapath & bandwidth of PC-800. So far though the benchmarks are not showing that real world apps are taking advantage of anything that says "Rambus" on it... yet. (or maybe never)Adding a second channel increases the bandwidth available - that means that large amounts of data need to be transferred, the total latency is decreased. When little bandwidth is needed latency is unchanged.
This is why the P4 gets so badly beaten at benchmarks where latency, rather than bandwidth, is important.
Replacing the RDRAM with, even single channel, DDR SDRAM would improve the performance at the benchmarks that are latency biased (most of them). Using dual channel DDR SDRAM would improve performance in all tests because of the lower latency and higher bandwidth (in some tests, the FSB would become the limiting factor).
It is possible to use techniques such as caches and pre-fetching to trade bandwidth for latency - however, P4s small cache doesn't seem to be sufficient for the latency penalty of RDRAM.
This is why the P4 gets so badly beaten at benchmarks where latency, rather than bandwidth, is important.
Replacing the RDRAM with, even single channel, DDR SDRAM would improve the performance at the benchmarks that are latency biased (most of them). Using dual channel DDR SDRAM would improve performance in all tests because of the lower latency and higher bandwidth (in some tests, the FSB would become the limiting factor).
It is possible to use techniques such as caches and pre-fetching to trade bandwidth for latency - however, P4s small cache doesn't seem to be sufficient for the latency penalty of RDRAM.
Rambus (the company) is the Worst thing to happen to the computer industry in the last decade... I wish terrorist would blow then up! *hint hint to all you terrorist*
hehe
hehe
What I really liked was the Q3 score. The benchmarks sold me. To bad I cant afford the system I would build. I must have a dual processor and over 256 megs ram. So that I dont have to sell my car I will go the way of 760mp and 800-900MHZ Tbird after christmas.
Havent you read what nVidia is doing with their Crush chipset, dual DDRAM channels, 128bit DDRAM. Who cares if you can maybe use 4 RDRAM chips on 4 channels when you can have PC2100 DDRAM at 128bit
RAMBUS SUCKS ANYHOW
RAMBUS SUCKS ANYHOW
I guess I missed that when I read about the crush chipset. that does sound pretty cool. Wonder if the crush chipset would be MPS compatible.
P4 reviews have convinced me that in order to keep up with memory performance with dual-channel PC800 Direct RAMBUS RAM, DDR platform needs to widen memory bus from 64 bits to 128 bits or considerably boost frequency. I am certain that Pentium IV would be noticeably slower on a traditional PC2100 DDR SDRAM platform than on dual-channel PC800 DRDRAM platform. P4 memory subsystem is built to work optimally with RAMBUS - looking at memory-dependant benches, very low latency L1 cache and L2 cache giving massive 48GB/s bandwidth seems to work wonders hiding RAMBUS's latency issues.
However, I believe that in the near future, DDR SDRAM will prevail. It's not propietary as RAMBUS, and chipsets utilizing 128bit memory (nVidia's "Crush" Athlon chipset for example) as well as higher frecuency DDR modules (150MHz - PC2600) are already in the works. Also aside from it's memory interface, P4 as a CPU completely fails to impress me.
However, I believe that in the near future, DDR SDRAM will prevail. It's not propietary as RAMBUS, and chipsets utilizing 128bit memory (nVidia's "Crush" Athlon chipset for example) as well as higher frecuency DDR modules (150MHz - PC2600) are already in the works. Also aside from it's memory interface, P4 as a CPU completely fails to impress me.
"So Rambus isnt as bad as we thought"
Sure with 4 RDRAM rimms you could cook a pizza in your tower as you work. That's not bad!
I read at Ars technica that RDRAMS are limited to 2 RIMMS to keep the latency down. As more RIMMS are added the latency gets worse due to the serial nature. Did they find a workaround with the 850 chipset?
Sure with 4 RDRAM rimms you could cook a pizza in your tower as you work. That's not bad!
I read at Ars technica that RDRAMS are limited to 2 RIMMS to keep the latency down. As more RIMMS are added the latency gets worse due to the serial nature. Did they find a workaround with the 850 chipset?
its only kickass on bandwidth. how many apps is solely dependent on bandwidth? any companies that has that many lawyers can't be good news.
<< It seems that when rambus is placed in pairs on the i850 its pretty kickass. >>
True but that doesn't stop the P4 from sucking big time
<< I have been reading that when the RDRam Dimms are placed in pairs on the i850 latency is effectively reduced because of the 32bit data pathway that is created. >>
Not quite true...latency is reduced, but not becuase of the fact that the data bus is wider...that just effects bandwidth. I think it has to do with more active pages or something like that...something to do with the nature of interleaving, not just the bus width.
<< My question is if you have all 4 slots full would the pathway become 64 it thus increasing performance even more? or would that require each memory bank to have 4 slots rather than 2. >>
Sweet..but no. Two of the RIMM slots are on channel 1, two of them are on Channel 2. The actual number of slots makes no difference (well there must be at least 1 slot per channel, and all channels probably need the same number but it could be 2 or 3 or 4 or 12 as long as each channel had the same). The i850 is a 2 channel chipset. It has 2 slots/channel. it's not a 4 channel, 1 slot/channel chipset. Besides even if it was it wouldn't help much Dual channel PC800 gives 3.2GB/s bandwidth which is exactly what the P4 has for FSB bandwidth so it is well matched. You probably woudln't gain a whole lot if you doubled the memory bandwidth without uppping the FSB bandwidth.
rambus isn't that bad right now, but pc800 is still more than pc2100 ddr ($200 vs $140 or so). PC700 is around $120 right now, so you could get dual of that and be running dual pc600 rambus which would still be more bandwith than a single channel pc2100 ddr. But there will be dual channel ddr boards, like the micron samba and the nvidia crush, so then ddr will probably win by then. The nvidia crush with 2 pc2600 ddrs will probably eat the i850 for lunch. VIA will probably come out with a dual channel chipset (just guessing) and i read that ALI is already prepping one, as well as ATI.
Wait until the "Crush" chipset comes out and we have dual channel DDR. Then we will see who's daddy.
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