Question So, Intel DOES "die harvest" after all... according to AT front-page article.

[VirtualLarry]

https://www.anandtech.com/show/13660/amd-athlon-200ge-vs-intel-pentium-gold-g5400-review/

* Intel harvests both 2+2 and 4+2 dies to make G5400 parts. It's impossible to know which one you have without removing the lid and measuring the die area.

Right under and in the comparison chart. Intel Pentium Gold 5400, it says is made from both 2-core, as well as 4-core dies (harvested).

I've personally speculated that Intel has been doing this for years, but the Intel fans on this forum all poo-pooed the idea, and claimed that Intel's yields "were so high that they didn't need to 'harvest'", and that "Intel's brand would be damaged, should consumers ever find out that they 'harvest'".

Well, finally, it's in writing, on AT's front page no less in an article.

So, Intel fans on this board, EAT CROW.

Edit: Honestly, it just makes good business sense to me. Done properly (secretly?), it shouldn't damage the brand at all. But it would be interesting, if truth-in-labeling laws apply to CPUs in that way, such that the packaging of those CPUs in retail, would be required to carry a sticker, "Intel B-stock".

 

[whm1974]

From reading that article I don't there there is any real difference with the two, aside from TDP.

 

[BigDaveX]

Intel has been doing this kind of thing since the Core 2 era, if not even earlier. It shouldn't come as a surprise to anyone that they don't throw away usable dies if they can be made to function as something lower-end.

 

[Spartak]

Yeah not sure why this is a surprise to anyone. Also, for a textbook harvested chip we already had the 8086K last year.

Scrap that, still early. Confused binning with harvesting (and assumed this was about the i9-9990XE).

 

[NTMBK]

"EAT CROW"? Chill out, Larry It's just computer parts, no need to take it so seriously.

 

[PotatoWithEarsOnSide]

I agree fully with the edit; makes sense it increase the effective yield by harvesting defective dies. I'm not sure how much scope there is for harvesting in low core count dies though.

 

[Insert_Nickname]

I thought this was more-or-less an open secret. I mean, why wouldn't they use a quad core die with perhaps only a defective core? There shouldn't be any difference at all in functionality between quad and dual core dies from the same generation.

Better to get -some- return, then just toss it in the bin. I'm more surprised we haven't seen tri cores from Intel, like AMD did. A 3C/6T product with the right specs and pricing could be attractive. Or could have been is perhaps more appropriate given today's market.

I agree fully with the edit; makes sense it increase the effective yield by harvesting defective dies. I'm not sure how much scope there is for harvesting in low core count dies though.

If there is only 2 cores, then yeah, that's going to be a problem. No single core* CPUs anymore, and good riddance to that.

On the other hand, with such a small die, yields should be excellent.

*The Celeron G470 was the last of the line. SB single core with HT.

 

[LTC8K6]

How could AMD or Intel afford to waste a die that could be saved and sold?

 

[DigDog]

WHY would AMD or Intel afford to waste a die that could be saved and sold.

There is no downside to you, consumer, if your 2-core CPU has 2 more, disabled cores on it. Why the worry?

Besides, brand reputation is established at the high end, far more than the budget end - that's why garbage like Renault races F1.

 

[bononos]

Would harvested

https://www.anandtech.com/show/13660/amd-athlon-200ge-vs-intel-pentium-gold-g5400-review/

....................
Edit: Honestly, it just makes good business sense to me. Done properly (secretly?), it shouldn't damage the brand at all. But it would be interesting, if truth-in-labeling laws apply to CPUs in that way, such that the packaging of those CPUs in retail, would be required to carry a sticker, "Intel B-stock".

Would there be a performance hit from harvested dies for the 2core/4 thread models?

 

[LTC8K6]

Would harvested


Would there be a performance hit from harvested dies for the 2core/4 thread models?

I can't see how there could be a performance hit.

 

[somethingclever]

I can't see how there could be a performance hit.

I don't know how intel does inter-core communication on that die, but there could be extra latency on the 4+2 vs 2+2 from extra hops the data needs to traverse.

 

[BigDaveX]

I don't know how intel does inter-core communication on that die, but there could be extra latency on the 4+2 vs 2+2 from extra hops the data needs to traverse.

Presumably they just disconnect the non-functional cores from the ring bus, leaving the two remaining cores communicating directly. And even if it had to poll the inactive cores, the latency penalty would most likely be extremely minimal.

 

[Mopetar]

Does it really matter if they do or not? As long as the product you get still functions within specifications, I don't see any problem.

Has anyone tried to see if it's possible to unlock any extra cores (if they're functional) if you get the 4-core version like you might be able to do with the X3 Athlon / Phenom chips?

 

[somethingclever]

Presumably they just disconnect the non-functional cores from the ring bus, leaving the two remaining cores communicating directly. And even if it had to poll the inactive cores, the latency penalty would most likely be extremely minimal.

That makes sense, but I still have questions... Is there any more information on how the ring bus works internally?

The ring bus is fully pipelined and so I would expect there to be something like registers at each node on the bus (or even in between). So even with a core disabled, there is would still be the extra "hop". I do agree with you that it'd be minimal regardless because they're so close together anyways.

 

[BigDaveX]

Has anyone tried to see if it's possible to unlock any extra cores (if they're functional) if you get the 4-core version like you might be able to do with the X3 Athlon / Phenom chips?

As far as I know, that's never been possible on Intel chips. And I don't think it's even been possible on any AMD chips since Bulldozer.

That makes sense, but I still have questions... Is there any more information on how the ring bus works internally?

The ring bus is fully pipelined and so I would expect there to be something like registers at each node on the bus (or even in between). So even with a core disabled, there is would still be the extra "hop". I do agree with you that it'd be minimal regardless because they're so close together anyways.

From a quick glance over articles relating to Sandy Bridge (where they first introduced the ring bus), it sounds like the bus is wired in parallel rather than in series, so presumably in instances where one or two cores aren't working they just cut the physical connection to the bus and put something to the effect of "cores at Ports A and B, ignore Ports C and D, they don't exist" in the chip's microcode. Admittedly, however, that's entirely my speculation.

 

[Insomniator]

Why do we care if a company harvests chips?

 

[somethingclever]

As far as I know, that's never been possible on Intel chips. And I don't think it's even been possible on any AMD chips since Bulldozer.


From a quick glance over articles relating to Sandy Bridge (where they first introduced the ring bus), it sounds like the bus is wired in parallel rather than in series, so presumably in instances where one or two cores aren't working they just cut the physical connection to the bus and put something to the effect of "cores at Ports A and B, ignore Ports C and D, they don't exist" in the chip's microcode. Admittedly, however, that's entirely my speculation.

I'm speculating just as much as you are ¯\_(ツ)_/¯

 

[Topweasel]

https://www.anandtech.com/show/13660/amd-athlon-200ge-vs-intel-pentium-gold-g5400-review/




Right under and in the comparison chart. Intel Pentium Gold 5400, it says is made from both 2-core, as well as 4-core dies (harvested).

I've personally speculated that Intel has been doing this for years, but the Intel fans on this forum all poo-pooed the idea, and claimed that Intel's yields "were so high that they didn't need to 'harvest'", and that "Intel's brand would be damaged, should consumers ever find out that they 'harvest'".

Well, finally, it's in writing, on AT's front page no less in an article.

So, Intel fans on this board, EAT CROW.

Edit: Honestly, it just makes good business sense to me. Done properly (secretly?), it shouldn't damage the brand at all. But it would be interesting, if truth-in-labeling laws apply to CPUs in that way, such that the packaging of those CPUs in retail, would be required to carry a sticker, "Intel B-stock".

VL it comes from AMD's time with the Phenom X3 and stuff.

Intel made this proclamation that they would never sell CPU's that failed tests in anyway. They were still reeling from the Pentium MMX and PIII 1.13GHz recalls (the later was supposedly only 100+ chips shipped mostly to reviewers).

But the truth is somewhere between AMD's binning and no binning at all. Shortly after the PIII coppermine release Intel changed up how they handled their fabs. They instituted processes for making sure all fabs being identical. No more shunning Malaysian serial numbers and hunting Costa Ricain serial number in OEM chip bins. Anyways by the time Intel had made that statement they were comfortable with their manufacturing and being able to make 100's of millions of chips a year helped with that, that they could pre-bin their wafers right away. After the pre-binning they could do the normal tests and bin for speed. That meant they would lazer off cache or cores well before actually figuring out if it was bad making so it never failed.

That said even that is long gone. On the server side Intel has three dies that they sell from 4-10 cores, 12-18 cores, 20-28 cores. None of them make sense without binning and no way Intel could risk throwing away a useable die on 28 core production line. Every chip on that line is thoroughly tested to make sure they can find the highest sku they can sell each die to maximize margin. They might be more willing then ever before to throw away 4c and 2c dies. But the days of them just pre-binning before testing is long gone on the chips that matter the most.

 

[Rifter]

Why do we care if a company harvests chips?

Objective people do not care.

Larry is right about one thing though the intel fanboys rabidly denied that intel harvested chips for the past several decades.

 

[Arachnotronic]

Objective people do not care.

Larry is right about one thing though the intel fanboys rabidly denied that intel harvested chips for the past several decades.

Proof? Seems like a straw man. Intel literally disables parts/features on chips all of the time. Look at the Xeon lineup or even something like 9700K which has cache disabled. Even the 9600K literally has two cores disabled.

 

[LTC8K6]

It may be that Intel, for a time, stayed away from using defective dies due to the problems that occurred, but then went back to the practice as things improved.

I always thought that prior to six core and up dies, there was basically a single 4 core die that was made into all of the chip variants - 2C/2T, 2C/4T, 4C/4T, and 4C/8T.

 

[VirtualLarry]

"EAT CROW"? Chill out, Larry It's just computer parts, no need to take it so seriously.

So sorry, Mr. Crow Avatar, I didn't mean it personally directed at you.

 

[BigDaveX]

Proof? Seems like a straw man. Intel literally disables parts/features on chips all of the time. Look at the Xeon lineup or even something like 9700K which has cache disabled. Even the 9600K literally has two cores disabled.

Heck, if you really want to go back, Intel has been disabling major components of their chips since at least around 1990, when they sold 486DXs with defective floating-point units as 486SXs.

 

[jpiniero]

It's rare for Intel to disable cores on desktop, but might just be a part of the shortage issue. I would expect this to be commonplace going forward however.

Proof? Seems like a straw man. Intel literally disables parts/features on chips all of the time. Look at the Xeon lineup or even something like 9700K which has cache disabled. Even the 9600K literally has two cores disabled.

You think they don't have a native 6 core die? I would be surprised.