Few comments. The cubic scaling only holds locally, because the F/V curve is not linear - it is rather a hyperbolic function, which has a zero/pole roughly at Vth. This means at half the frequency you might need more or less than half the voltage - depending on what your reference point is.
Finally, even if we assume, that your calculation is correct, ( 2 * (1/2)^3) = 1/4 and not just half.
Late night brain dumb on the 1/4 vs 1/2 part. As for treating it as linear, it's a simplification that's close enough for teaching a casual person. It's just not realistic to measure all the components that go into a V/F curve, so you need a simplified model. Vth on its own can vary >100mV chip-to-chip, and the curve also depends heavily on the design and process. Once you get to a certain point, the curve inflects due to paths becoming wire-dominated and becomes way worse than linear. For example, the A12
V/F Curve shows a 7x increase in power going from 1.2ghz (or just a bit less) to 2.4ghz (or just a bit less), which is practically cubic. Then once you get above 0.9v it explodes. To me, this indicates the core team designed primarily around the 0.6v and 0.9v corners and didn't do much if any work on anything above that, so the design's routes just don't let frequency scale higher.
This I am not sure of. For one, I have heard that the prime core in chips like the SD 865 use 'relaxed HP libraries'. The SD 865 has 4× A77 cores. But one A77 core uses the said HP library to enable higher peak frequencies and thus act as a 'prime core'.
In addition I am also aware that some nodes have such a thing as a UHD library (Ultra High Density). I will try to post the source if I can find it.
I HIGHLY doubt the SD865 has any 3-fin cells in it. If it does, Qualcomm's dumb. They might have synthesized at a tighter frequency and used 8T SRAM instead of 6T, but that's an entirely different thing altogether.
As for UHD, that's a new thing for N3E. N3E has UHD (1+2 fin), HD (2-fin), and HP (3+2 fin) arrangements. UHD and HP are hybrid row, meaning they alternate between 2-fin and 1-fin (UHD) or 3-fin (HP). Hybrid row introduces a lot of design challenges, mainly focused around legalization, multi-row cells, and achieving high utilization (tool may pack certain rows but leave others empty). As a result, you get dramatically higher runtime on the UHD or HP libaries compared to regular HD. Anyone chasing maximum power/area scaling will still want to use UHD, but for performance-focused parts there will still be plenty of demand for HD. Anyone using HP is an idiot because it doesn't give that much performance, and with HD you can spin your design more times to get better convergence on timing.
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