Simplified 256-bit SDRAM controllers

MadRat

Lifer
Oct 14, 1999
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Couldn't improved bus to bus links like HT be used to simplify main memory controllers? I would think that you could tie in four banks of SDRAM or DDR RAM into a single HT link to the memory controller. Pure one-way, two-way, three-way, or four-way increments would be possible by populating each memory bank. This could also make it so that every stick of memory could run differing sizes as long as they all were timed at the same speed.

Is this plausible or would you still need some type of NUMA interface?
 

JattKhalsa

Junior Member
Jul 16, 2001
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Theoretically it can be done, but think about the cost of implementing a 256 or even a 64 bit HT link. Who would wanna pay $400 for a motherboard with just a faster FSB. Also the complexity of a DRAM controller would increase massively.:cool:
 

MadRat

Lifer
Oct 14, 1999
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The HT bus would still be its normal 64-bit self. Only the controller that ties the four memory banks together would be 256-bit.
 

CTho9305

Elite Member
Jul 26, 2000
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how is this different from the nForce's dual-channel deal, and RDRAM's multiple-channel setup?
 

CTho9305

Elite Member
Jul 26, 2000
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<< Dual Channel requires a matched pair of SDRAM DIMMs. >>


so this is the same basic idea without that restriction?
 

MadRat

Lifer
Oct 14, 1999
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It would remove the need to populate in pairs and to match exact sizes between each DIMM.
 

Sohcan

Platinum Member
Oct 10, 1999
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<< It would remove the need to populate in pairs and to match exact sizes between each DIMM. >>

*cough*
The nForce has neither of those restrictions. ;)


<< When we heard about the 128-bit memory interface on the nForce, we assumed that memory would have to be installed in matched pairs, but NVIDIA's tech docs state that this is not the case. Since each memory bank has its own memory controller, the modules can be different sizes and even different speeds. A Single Intelligent Arbiter decides which memory controller will handle what data. Nevertheless, our guess is that performance will be better if there is an equal amount of memory in each bank, since this will allow for the interleaving of data evenly between the two banks. >>