Shanghai or Bulldozer talk?

[Idontcare]

Originally posted by: bryanW1995
charlie isn't exactly the best source for info

This is true but only because Charlie doesn't exactly have access to the highest quality sources of information.

I have seen cases where Charlie reported on SUN processors and I knew for a fact because I had insider knowledge that (a) the "information" was patently false, and (b) who the egomaniacal idiot was (on my side of the fence) who fancied themselves as having credible knowledge to leak to Charlie.

Just as you see here on the forums, there are people "in the know" and then there are people who believe that because they get a paycheck from a certain employer then they suddenly are endowed with all the insider info on every aspect of the employer's business model.

It never ends, people talking up there area of knowledge. And Charlie has to filter through that crap when he gets his "tips". Sure some journalists are willing to filter thru the obvious BS more so than others, and some are just so illiterate of the industry that they are easily dazzled by the BS that they can't actively filter.

And then sometimes they get the real McCoy and they turn out a beautiful piece on reality but it seems so absurd that everyone lamblasts them as being drunk. (I'm guilty of doing this too)

BTW here is a Charlie article that is literally spot-on in every sentence from what I know. He got himself some good sources on this one. http://www.theinquirer.net/gb/...2/18/sun-tsmc-fabulous

 

[bryanW1995]

I shouldn't lump charlie with fuad, for all I know he ran fuad out on a rail...that was a good article, too.

 

[Idontcare]

Originally posted by: bryanW1995
I shouldn't lump charlie with fuad, for all I know he ran fuad out on a rail...that was a good article, too.

True, Fraud is whole other category of unethical self-promoting shills who like to label themselves as freelance journalists.

That whole fabricated screenshots of futuremark debacle will never allow Fraud to claim any credibility, ever. You can bet he got his ass fired over that, err I mean he left TheINQ to persue personal interest outside the job function along with Phil Hester.

 

[Kuzi]

A question here, if AMD releases Shanghai at a max frequency of say 3.0GHz, how much of an improvement would they get from moving to Hi-K process compared to their current SOI process. Can we assume 3.4-3.5GHz for Hi-K?

 

[Idontcare]

Originally posted by: Kuzi
A question here, if AMD releases Shanghai at a max frequency of say 3.0GHz, how much of an improvement would they get from moving to Hi-K process compared to their current SOI process. Can we assume 3.4-3.5GHz for Hi-K?

Hi-k process technology is orthogonal to SOI technology, one does not exclude/supplant/preclude the other.

Hi-k process technology is not orthogonal to SiON gate oxide technology (so-called plasma nitrided gate oxide)...so having a Hi-k gate oxide will supplant the existing SiON in the transistors (at least in Hi-k's current implementation).

However Hi-k as a process technology on its own is problematic in that the electron mobility curve is severely degraded. To counter this degradation the hi-k gate oxide must be paired with a gate that does not rely on boron doping for its electrical characteristics (as traditional polysilicon gates do). This is why Intel paired their Hi-k gate oxide with metal gates, and this is also why IBM announced similiar intentions.

So if I were to answer your question specifically as you asked it, I suspect Shanghai would suffer significant Fmax (clockspeed) degradation if they replaced SOI with Hi-k. If you meant the SiON, then I still suspect Shanghai would suffer significant clockspeed degradation in that case as well.

If you meant the replacement of SiON with Hi-k and the replacement of polysilicon gates with metal gates, then I suspect they won't secure higher clockspeed (nor slower ones) but will significantly reduce their power consumption at any given clockspeed.

(remember HK/MG process technology is used to combat current leakage, not necessarily to make transistors switch faster...but of course the leakage budget could be "spent" to increase switching speed at the expense of increased leakage and higher power consumption per clock)

 

[dmens]

Originally posted by: Idontcare
remember HK/MG process technology is used to combat current leakage, not necessarily to make transistors switch faster...but of course the leakage budget could be "spent" to increase switching speed at the expense of increased leakage and higher power consumption per clock

absolutely on the spot there. from the intel side, the width knob was almost totally turned toward the leakage reduction as opposed to drive strength gain.

 

[Phynaz]

Originally posted by: Viditor

Originally posted by: bryanW1995

Will AMD be competing in the high end cpu and/or gpu market?

They already do...

Did amd just announce the phenom 10450 @ 3 ghz??? how'd I miss that???

What you missed m8 is that Intel still can't build an Enterprise server yet...

They really need Nehalem to work!

Funny about that, you say Intel can't build and Enterprise server yet, but Itanium has 50% market share in the top end.

Perhhaps your definition of Enterprise server is different than that of the people who actually buy them.

 

[CTho9305]

Originally posted by: Idontcare

Originally posted by: Kuzi
A question here, if AMD releases Shanghai at a max frequency of say 3.0GHz, how much of an improvement would they get from moving to Hi-K process compared to their current SOI process. Can we assume 3.4-3.5GHz for Hi-K?

Hi-k process technology is orthogonal to SOI technology, one does not exclude/supplant/preclude the other.

Hi-k process technology is not orthogonal to SiON gate oxide technology (so-called plasma nitrided gate oxide)...so having a Hi-k gate oxide will supplant the existing SiON in the transistors (at least in Hi-k's current implementation).

However Hi-k as a process technology on its own is problematic in that the electron mobility curve is severely degraded. To counter this degradation the hi-k gate oxide must be paired with a gate that does not rely on boron doping for its electrical characteristics (as traditional polysilicon gates do). This is why Intel paired their Hi-k gate oxide with metal gates, and this is also why IBM announced similiar intentions.

So if I were to answer your question specifically as you asked it, I suspect Shanghai would suffer significant Fmax (clockspeed) degradation if they replaced SOI with Hi-k. If you meant the SiON, then I still suspect Shanghai would suffer significant clockspeed degradation in that case as well.

If you meant the replacement of SiON with Hi-k and the replacement of polysilicon gates with metal gates, then I suspect they won't secure higher clockspeed (nor slower ones) but will significantly reduce their power consumption at any given clockspeed.

(remember HK/MG process technology is used to combat current leakage, not necessarily to make transistors switch faster...but of course the leakage budget could be "spent" to increase switching speed at the expense of increased leakage and higher power consumption per clock)

See also my post here.

 

[Viditor]

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: bryanW1995

Will AMD be competing in the high end cpu and/or gpu market?

They already do...

Did amd just announce the phenom 10450 @ 3 ghz??? how'd I miss that???

What you missed m8 is that Intel still can't build an Enterprise server yet...

They really need Nehalem to work!

Funny about that, you say Intel can't build and Enterprise server yet, but Itanium has 50% market share in the top end.

Perhhaps your definition of Enterprise server is different than that of the people who actually buy them.

You are kidding here, aren't you?
As of Q107, Itanium systems had only half the systems that Sun Sparc had, and 28% of the IBM Power systems...
AMD is currently second to IBM, but is still gaining on them.
This was according to the IDC report I have in front of me right now...

I think what you may have meant was that Itanium has grown 50%...which is a very different matter.

 

[Phynaz]

Like I said, your definition is just different.

AMD systems don't compete in anywhere near the same class as the high end Itanium systems.

You're the one who is kidding if you think HP makes an AMD equivalent to Integrity Nonstop or IBM makes an AMD equivalent to P595. Sun doesn't build an AMD equivalent to M9000. Unisys only offers 8 sockets for AMD servers, but 32 for Itanium. Let's take a look at NEC, nope no AMD equivalent to the 5800/1000 over there. Fujitsu? No, Can't find any AMD processors in their high end equipment either.

Those are the systems that run enterprises.

I'm not saying that enterprises don't run lots of commodity x86 systems, but they don't run the business on them.

AMD market share in the class I'm talking about is pretty much zero.

 

[Viditor]

Originally posted by: Phynaz
Like I said, your definition is just different.

AMD systems don't compete in anywhere near the same class as the high end Itanium systems.

You're the one who is kidding if you think HP makes an AMD equivalent to Integrity Nonstop or IBM makes an AMD equivalent to P595. Sun doesn't build an AMD equivalent to M9000. Unisys only offers 8 sockets for AMD servers, but 32 for Itanium.

Those are the systems that run enterprises.

I'm not saying that enterprises don't run lots of commodity x86 systems, but they don't run the business on them.

AMD market share in the class I'm talking about is pretty much zero.

I don't think you understand modern servers...
Yes, AMD currently has up to an 8 socket (32 core) system on a single frame...
But, AMD is incredibly NUMA aware and operates in cluster configurations extremely well!
Any systems with 4 sockets (16 cores) or more is pretty much destined for the Enterprise market...unless you can think of an application in small business you'd actually need that for?

BTW, a HUGE amount of Enterprise is done in x86...something that Itanium really sucks at and current Intel x86 is not good at (in 4 socket or greater configurations). Hence my comment that Nehalem better perform the way it's expected to...

Edit: One last thing...the "class" you mention would be better called a niche. It is a very small percentage of todays Enterprise market.

 

[Phynaz]

Okay, you're right, you know more about servers than all the companies I just listed. I guess they have all miss clasified their AMD offerings as SMB servers.

Oh, and the P595 I listed? I'm taking delivery of one tomorrow, so I happen to know a thing or two about modern servers. At least I had better, because it cost $1.4M.

But again, Itanium sucks at enterprise? really? You keep repeating it over and over, as if that will make it true. But yet you provide no evidence.

Here's something you don't know: How tiresome it is when someone refuses to concede an argument.

 

[Phynaz]

To reply to your edit, since you quoted IDC, they say the 2007 server market was $15.7B, while x86 was was $7.8B of that, just under half.

I wouldn't call > 50% of the total market a "niche".

Oh well, like Jones said, for someone who claims to follow this so closely...

I'll bow out of this one now, feel free to have the last word, again.

 

[Kuzi]

Originally posted by: Idontcare
If you meant the replacement of SiON with Hi-k and the replacement of polysilicon gates with metal gates, then I suspect they won't secure higher clockspeed (nor slower ones) but will significantly reduce their power consumption at any given clockspeed.

(remember HK/MG process technology is used to combat current leakage, not necessarily to make transistors switch faster...but of course the leakage budget could be "spent" to increase switching speed at the expense of increased leakage and higher power consumption per clock)

Sorry I meant Hi-K/MG

From what I understand the current Barcelona/Phenom design does have a severe leakage problem. That is why when you OC for example, at a certain point (after a few hundred MHz) the required voltage increases tremendously and the power consumption increases exponentially with it.

AMD said to expect a 15% reduction in power consumption from moving to their 45nm process, that does not seem enough to compete with Intel. So if adding Hi-K/MG helps with leakage and power consumption as you?ve mentioned then it should help K10.5 reach a bit higher speeds with maybe only a slight increase in power consumption.

To me K10.5 being released at 3.4GHz does seem doable, just not initially, and who knows what Intel will have by that time.

 

[Idontcare]

Originally posted by: Kuzi

Originally posted by: Idontcare
If you meant the replacement of SiON with Hi-k and the replacement of polysilicon gates with metal gates, then I suspect they won't secure higher clockspeed (nor slower ones) but will significantly reduce their power consumption at any given clockspeed.

(remember HK/MG process technology is used to combat current leakage, not necessarily to make transistors switch faster...but of course the leakage budget could be "spent" to increase switching speed at the expense of increased leakage and higher power consumption per clock)

Sorry I meant Hi-K/MG

From what I understand the current Barcelona/Phenom design does have a severe leakage problem. That is why when you OC for example, at a certain point (after a few hundred MHz) the required voltage increases tremendously and the power consumption increases exponentially with it.

AMD said to expect a 15% reduction in power consumption from moving to their 45nm process, that does not seem enough to compete with Intel. So if adding Hi-K/MG helps with leakage and power consumption as you?ve mentioned then it should help K10.5 reach a bit higher speeds with maybe only a slight increase in power consumption.

To me K10.5 being released at 3.4GHz does seem doable, just not initially, and who knows what Intel will have by that time.

You got it right.

The issue at this poignant time is that Hik/MG is a disruptive technology at the process development level.

You don't evolve an existing process into becoming a HiK/MG process. You literally throw away 30 yrs of process technology evolution and attempt to start over but with the requirement that you must hit the ground running so fast and hard that you manage to trump the performance of that 30yr evolved technology.

Intel did this, IBM and AMD are taking just a bit longer which is no surprise when you balance out effects of R&D budgets on timelines.

(the transition from aluminum to copper is another example of truly disruptive process technology, and AMD led the industry down that rabbit-hole at 180nm node thanks in part to collaboration with Motorola at the time)

Now what AMD has to their advantage is that once they get on the other side of this disruptive transistion and they get HiK/MG released and shoehorned into their 45nm node then making iterative improvements to the technology via CTI will make their transition from 45nm to 32nm all the faster and easier as they can get back to focusing on shrinking and evolving rather than mastering disruptive technologies for a few more nodes thereafter (at least till 16nm).

I'm actually pretty bullish on AMD at the moment, albeit not for short-term prospects but more for the mid-term (2-3 yrs). The CTI model stands to maximize their transition to immersion litho and HiK/MG.

And AMD's antitrust lawsuit with Intel is actually setting the stage to require the DOJ to break Intel up should AMD go bankrupt or make a convincing argument they must exit the x86 industry as they can't compete with a monopoly. The groundwork is laid out and there is no way DOJ can ignore the antitrust issue, whether AMD was right about Intel's actions (and scores billions in court awards) or they are right about the fact no one can compete with Intel now...there is no way out of this for Intel unless they convince the US's congress to repeal anti-trust laws.

Intel is one node away from winning the battle and losing the entire fracking war. They best study what happened to Ma Bell and RCA, you can get away with it for a couple decades but eventually the outcome is the entire undoing of everything you built-up.

 

[Kuzi]

Originally posted by: Idontcare
The issue at this poignant time is that Hik/MG is a disruptive technology at the process development level.

You don't evolve an existing process into becoming a HiK/MG process. You literally throw away 30 yrs of process technology evolution and attempt to start over but with the requirement that you must hit the ground running so fast and hard that you manage to trump the performance of that 30yr evolved technology.

Ok since Hi-K/MG is disruptive and you have to start from scratch, wouldn't that mean that any technology developed to work on SOI may not work on Hi-K/MG?

Let me give an example: AMD licensed Z-RAM (Zero Capacitor DRAM) about 2.5 years ago, Z-RAM technology gives five times the density of standard SRAM while decreasing power consumption.

I had thought AMD would implement Z-RAM into their future processors instead of SRAM (ex. L3). But Z-RAM uses SOI, doesn't that mean it can't be implemented if AMD moves to Hi-K/MG?

Just to show how much benefit Z-RAM can have, if we take Shanghai die size as 243mm2 (according to Hans de Vries). Lets say 83mm2 (about 34%) of the die size is for the 6MB L3 cache in Shanghai. 6MB of Z-RAM would take 1/5 that size so about 17mm2:

Propus, K10.5 w/o L3: 243mm2-83mm2= 160mm2
Shanghai, K10.5 6MB L3 SRAM: = 243mm2
Shanghai+6MB L3 Z-RAM: 160mm2+17mm2= 177mm2
Shanghai+12MB L3 Z-RAM: 160mm2+34mm2= 194mm2
Shanghai+24MB L3 Z-RAM: 160mm2+68mm2= 228mm2

Of course these numbers are not very accurate, but they do show that Z-RAM can reduce die size (cost) a lot while also reducing power consumption. Shanghai with 24MB L3 Z-RAM would still be smaller than the "normal" Shanghai with 6MB L3 cache. Though there is still a question mark whether Z-RAM is as fast as SRAM.

There is another technology called eDRAM, developed by IBM, meaning AMD has access to it: "IBM?s new eDRAM technology, designed in stress-enabled 65nm SOI using deep trench, dramatically improves on-processor memory performance in about one-third the space with one-fifth the standby power of conventional SRAM (static random access memory)."

Any thoughts on Z-RAM and eDRAM, can/will AMD use any of them for future processors. Obviously the biggest benefit of using them would be die size decrease, meaning more CPUs produced per wafer, more money for AMD, and cheaper processors for us

 

[myocardia]

Originally posted by: Kuzi
Ok since Hi-K/MG is disruptive and you have to start from scratch, wouldn't that mean that any technology developed to work on SOI may not work on Hi-K/MG?

While I don't happen to have a link, AMD said awhile back that HiK/MG won't work on SOI. Now, things change fairly fast in this industry, but that's the last I heard about it.

Originally posted by: Idontcare
Intel is one node away from winning the battle and losing the entire fracking war. They best study what happened to Ma Bell and RCA, you can get away with it for a couple decades but eventually the outcome is the entire undoing of everything you built-up.

I couldn't agree more. I'm just hoping it happens with Micro$oft sooner, rather than later, but that's another story altogether.

 

[Idontcare]

Originally posted by: myocardia

Originally posted by: Kuzi
Ok since Hi-K/MG is disruptive and you have to start from scratch, wouldn't that mean that any technology developed to work on SOI may not work on Hi-K/MG?

While I don't happen to have a link, AMD said awhile back that HiK/MG won't work on SOI. Now, things change fairly fast in this industry, but that's the last I heard about it.

HiK/MG has nothing really to do with SOI, if AMD was ever attributed with this statement in press then I highly suspect it was quoted out of context and that there were some clarifiers before and after such a statement.

I can imagine that a statement along the lines of "due to SOI, the fabrication steps involved in forming HiK/MG based transistors is more tenacious owing to thermal budget considerations" etc etc. But one technology really has no first-order bearing on the other.

Originally posted by: myocardia

Originally posted by: Idontcare
Intel is one node away from winning the battle and losing the entire fracking war. They best study what happened to Ma Bell and RCA, you can get away with it for a couple decades but eventually the outcome is the entire undoing of everything you built-up.

I couldn't agree more. I'm just hoping it happens with Micro$oft sooner, rather than later, but that's another story altogether.

Microsoft is being far more crafty about how they are walking the tightrope between antitrust action and continuing onwards with being a tolerated monopoly. Specifically they have been sure to not put Apple into the same dire straits that Intel has unintelligently sought to put AMD. Microsoft sees the value in having an Apple competitor throwing "Hi I'm a computer" ads onto TV...you won't see Microsoft trying to trounce Apple into the ground like Intel is doing.

It's a little more savvy an approach, keep an eye on the profits and your competition in check but don't be so stupid as to kill the entire food chain out of nothing but corporate ego and pride merely to watch the DOJ disassemble you thereafter.

Originally posted by: Kuzi
I had thought AMD would implement Z-RAM into their future processors instead of SRAM (ex. L3). But Z-RAM uses SOI, doesn't that mean it can't be implemented if AMD moves to Hi-K/MG?
.
.
.
There is another technology called eDRAM, developed by IBM, meaning AMD has access to it: "IBM?s new eDRAM technology, designed in stress-enabled 65nm SOI using deep trench, dramatically improves on-processor memory performance in about one-third the space with one-fifth the standby power of conventional SRAM (static random access memory)."

Any thoughts on Z-RAM and eDRAM, can/will AMD use any of them for future processors. Obviously the biggest benefit of using them would be die size decrease, meaning more CPUs produced per wafer, more money for AMD, and cheaper processors for us

To my knowledge ZRAM (ver2) is just as functional with SOI using HK/MG as without HK/MG. I've seen nothing to the contrary be published or discussed, and there is nothing in the device physics itself that precludes the use of HK/MG on SOI.

However, to be sure there is something undesirable about ZRAM as absolutely no one uses it in any production device whatsoever. You don't have a resume with that many "pros" and yet have zero job offers...something is rotten in denmark when it comes to ZRAM, I just haven't heard anyone give it any serious bad press, ever.

eDRAM got lots of bad press in terms of it being ridiculously slow. That one was very much a flash in the pan in the press and then you just never heard much more about it (and rightfully so).

I'd love to see AMD do something revolutionary with their cache structure to really mix things up, be it ZRAM or eDRAM or something else...but the fact they haven't strayed from mainstream process technology since their foray into copper BEOL and SOI FEOL.

 

[Kuzi]

True but we can't expect a new technology to be announced and then a few months later see it in retail products. Especially when talking about new memory, cache etc.

It takes a few years to show up if ever. I read an article about Z-RAM yesterday, but can't find the link now, it said to expect products using Z-RAM in 2010. Looking at the revised AMD Roadmap, in 1H 2010 they will release Magny-Cours, K10.5 based 12 core CPU with 12MB L3 cache. That's still on a 45nm process. So unless they can get much higher cache density compared to what they have now, how can they release such a beast without using Z-RAM, eDRAM or something similar.

eDRAM was announced only last year, so it might be a while before we see products based on it. I didn't know about it's slowness problems, I read it's specs and the latency was 1.5ns.

 

[Kuzi]

Originally posted by: Idontcare
To my knowledge ZRAM (ver2) is just as functional with SOI using HK/MG as without HK/MG. I've seen nothing to the contrary be published or discussed, and there is nothing in the device physics itself that precludes the use of HK/MG on SOI.

That is good news, I've checked and you are right, you can incorporate Hi-K/MG with SOI technology. IBM is already working on Hi-K/MG+SOI at 32nm.

 

[bryanW1995]

Originally posted by: Phynaz
Okay, you're right, you know more about servers than all the companies I just listed. I guess they have all miss clasified their AMD offerings as SMB servers.

Oh, and the P595 I listed? I'm taking delivery of one tomorrow, so I happen to know a thing or two about modern servers. At least I had better, because it cost $1.4M.

But again, Itanium sucks at enterprise? really? You keep repeating it over and over, as if that will make it true. But yet you provide no evidence.

Here's something you don't know: How tiresome it is when someone refuses to concede an argument.

uh, phynaz, heh heh, um, sorry about any bad things that I might have said about you in the past. do you think you could help me with a minimal system, say a skulltrail with a couple of cpus and some fb-dimms? I'll supply the gpu and psu...

 

[Phynaz]

LOL!

You know, now that I think about it, I don't know if any the boxes we are buying use fb-dimms...I'm going to have to look that up!

 

[Idontcare]

Originally posted by: Kuzi
True but we can't expect a new technology to be announced and then a few months later see it in retail products. Especially when talking about new memory, cache etc.

It takes a few years to show up if ever. I read an article about Z-RAM yesterday, but can't find the link now, it said to expect products using Z-RAM in 2010.

My point is simply that the proof of the pudding is in the eating...if ZRAM (or eDRAM) were all that they are talked up to be then you'd see them in products a whole lot sooner rather than later.

And ZRAM is way late to the "sooner" party so I am already writing this technology off as having some unseemly bad things about it that just have never been publicized yet.

Originally posted by: Kuzi
Looking at the revised AMD Roadmap, in 1H 2010 they will release Magny-Cours, K10.5 based 12 core CPU with 12MB L3 cache. That's still on a 45nm process. So unless they can get much higher cache density compared to what they have now, how can they release such a beast without using Z-RAM, eDRAM or something similar.

Magny-Cours is going to be an MCM'ed package with two discreet chips inside.

Nothing revolutionary there, proven technology distributed within a traditional package.

Originally posted by: Kuzi
eDRAM was announced only last year, so it might be a while before we see products based on it. I didn't know about it's slowness problems, I read it's specs and the latency was 1.5ns.

eDRAM has been discussed for years, it was "invented" in 1996. Here's an EETimes article from 2003 discussing the early days. http://www.eetimes.com/story/OEG20030414S0040

Don't get me wrong, eDRAM is used in products, I believe it is used extensively throughout the gaming console industry. But the fact it never hit the PC industry is very telling IMO. For example the specs of 1.5ns latency...what you don't get told in that part of the story is what trade-offs are made in order to minimize the latency to attain such seemingly promising numbers. The layout gets ballooned up in size, you lose your density advantage, or the devices are tweaked to run faster but at ridiculous leakage rates, or require operating voltages that are absurd, or the worst offense of all they become >1 mask adder components and the mask expense plus cycle-time delay thru the fab makes it a non-starter.

So I go back to the pudding, the proof is in the eating and when you don't see a particularly "promising" technology ever make it into the mainstream for years and years (holographic storage anyone, how about some flying cars?) then its usually because all you ever heard was the marketing hype that spins only the positives, meanwhile there are some real devils in the details that prevent the technology from ever being practical from day one.

 

[Kuzi]

Originally posted by: Idontcare
Magny-Cours is going to be an MCM'ed package with two discreet chips inside.

Nothing revolutionary there, proven technology distributed within a traditional package.

My worry here is about it's size, not necessarily the ability to produce it. If we take Shanghai as an example, it will be about 243mm2. Add 8 more cores and 6MB more cache, that will make it at least 650mm2 total size. A 200W TDP CPU anyone?

About eDRAM, you can check this link IBM Reveals Breakthrough eDRAM, it's from last year. They mentioned that:"The technology is expected to be a key feature of IBM?s 45nm microprocessor roadmap and will become available beginning in 2008."

Anyways if IBM does implement eDRAM in their newer processors this year, then it would mean they got enough benefits to use it. And AMD can follow suit.

 

[Idontcare]

Originally posted by: Kuzi

Originally posted by: Idontcare
Magny-Cours is going to be an MCM'ed package with two discreet chips inside.

Nothing revolutionary there, proven technology distributed within a traditional package.

My worry here is about it's size, not necessarily the ability to produce it. If we take Shanghai as an example, it will be about 243mm2. Add 8 more cores and 6MB more cache, that will make it at least 650mm2 total size. A 200W TDP CPU anyone?

About eDRAM, you can check this link IBM Reveals Breakthrough eDRAM, it's from last year. They mentioned that:"The technology is expected to be a key feature of IBM?s 45nm microprocessor roadmap and will become available beginning in 2008."

Anyways if IBM does implement eDRAM in their newer processors this year, then it would mean they got enough benefits to use it. And AMD can follow suit.

BTW I am 100% with you in thinking that AMD needs to do something revolutionary again (first copper was good, move to SOI was good, but scooped on HK/MG not so good) to get some kind of leg-up in this "yes we are a year behind Intel in releasing our nodes, but when we do release them they are more aggressive and more advanced" cycling.

45nm needs to be HK/MG plus ULK plus something...that something could be eDRAM or ZRAM, idontcare, but they need something!