I was having a conversation with a computer guru today, I mentioned that the more cache on a CPU die the higher the temps would be, but having less cache would decrease temps and allow higher OC. He laughed at me as if I was some idiot noob. He says cache makes no difference. Who is right?
Settle an argument.
- Thread starter NoStateofMind
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VirtualLarry
No Lifer
- Aug 25, 2001
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More cache = more transistors switching = more waste heat. Less cache means that for a given TDP budget, the chip could be clocked higher (if capable).
yeah. or any other program. the cache is barely sipping power when compared to the rest of the core.
lopri
Elite Member
- Jul 27, 2002
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Interesting. I appreciate the enlightenment. I would like a clarification, however.
You said above;
Then;
Which is it? I assume it's the latter?
You said above;
This sounds as if cache isn't much of a factor for clocking/TDP because it's not used as much it should. (?)
Then;
This sounds as if cache isn't much of a factor for clocking/TDP even when it's fully used because it just doesn't need much power.
Which is it? I assume it's the latter?
both actually. when i said the cache is "silent most of the time", i meant that even when the cache is fully loaded architecturally, there is very little electrical activity, specifically, most of the transistors are not switching.
The additional cache actually produces more power consumption, but not as significant compared with the rest of the core. That doesn't mean it doesn't matter.
More cache means more transitors, therefore more power consumption. The cache is a set of SRAM cells which are composed by CMOS transistors. In order for those cells to store information a lot of transistors have to be active and therefore drawing current from the supply.
Considering a more general situation, for example, let's suppose we have a N-way associative cache. For a larger cache size more sets of blocks it will have. Then when looking for a block in the cache, the possible candidate blocks are checked in parallel. So for larger caches, more blocks are checked simultaneously, thus more switching logic is needed which also contributes to power consumption.
However for CMOS submicron technologies working at high frequencies (in this case GHz) the static power is considered to have a small contribution (10%) compared with the dynamic power component (90%). The cache memory will remain in steady state (with no switches) at least that a cache miss occur. That would force to dismiss data from a block and to bring another block from memory, which would actually mean switching of the logic states of some SRAM cells. Thus the power consumption of the cache depends greatly of the frequency of cache misses.
That is why additional power consumption generated by additional cache is considered to be small compared to the switching activity of the rest of the functional blocks of the core. That doesn't mean it doesn't matter. It DOES matter, as the power consumption is critical and considering that almost the half of CPU area is occupied by the cache (see a core2 chip layout). That is why lots of cache can't be added happily without having the power consumption trade off.
More cache means more transitors, therefore more power consumption. The cache is a set of SRAM cells which are composed by CMOS transistors. In order for those cells to store information a lot of transistors have to be active and therefore drawing current from the supply.
Considering a more general situation, for example, let's suppose we have a N-way associative cache. For a larger cache size more sets of blocks it will have. Then when looking for a block in the cache, the possible candidate blocks are checked in parallel. So for larger caches, more blocks are checked simultaneously, thus more switching logic is needed which also contributes to power consumption.
However for CMOS submicron technologies working at high frequencies (in this case GHz) the static power is considered to have a small contribution (10%) compared with the dynamic power component (90%). The cache memory will remain in steady state (with no switches) at least that a cache miss occur. That would force to dismiss data from a block and to bring another block from memory, which would actually mean switching of the logic states of some SRAM cells. Thus the power consumption of the cache depends greatly of the frequency of cache misses.
That is why additional power consumption generated by additional cache is considered to be small compared to the switching activity of the rest of the functional blocks of the core. That doesn't mean it doesn't matter. It DOES matter, as the power consumption is critical and considering that almost the half of CPU area is occupied by the cache (see a core2 chip layout). That is why lots of cache can't be added happily without having the power consumption trade off.
I agree with dmens and cdbular. Compared to the CPU cores, on mainstream desktop CPU's, the cache power is pretty small. If you ever look at a CPU thermal map, the cache always shows up as blue (cool) compared to the execution units.
That said, cache isn't very active, but gate leakage current can start to add up. The CPU's that I work on have a lot of cache (24MB), and all that cache does start to add up after a while. You can use circuit and process tricks to reduce this leakage (sleep transistors, separate cache voltage supplies, longer gates, low Vt FETs, variable oxide thickness) but if you are planning on using it, then it will eat power - but slowly.
Welcome, cdbular. Impressive first post.
Patrick Mahoney
Circuit Design Engineer
Enterprise Processor Division
Intel Corp.
That said, cache isn't very active, but gate leakage current can start to add up. The CPU's that I work on have a lot of cache (24MB), and all that cache does start to add up after a while. You can use circuit and process tricks to reduce this leakage (sleep transistors, separate cache voltage supplies, longer gates, low Vt FETs, variable oxide thickness) but if you are planning on using it, then it will eat power - but slowly.
Welcome, cdbular. Impressive first post.
Patrick Mahoney
Circuit Design Engineer
Enterprise Processor Division
Intel Corp.
Originally posted by: pm
I agree with dmens and cdbular. Compared to the CPU cores, on mainstream desktop CPU's, the cache power is pretty small. If you ever look at a CPU thermal map, the cache always shows up as blue (cool) compared to the execution units.
That said, cache isn't very active, but gate leakage current can start to add up. The CPU's that I work on have a lot of cache (24MB), and all that cache does start to add up after a while. You can use circuit and process tricks to reduce this leakage (sleep transistors, separate cache voltage supplies, longer gates, low Vt FETs, variable oxide thickness) but if you are planning on using it, then it will eat power - but slowly.
Welcome, cdbular. Impressive first post.
Patrick Mahoney
Circuit Design Engineer
Enterprise Processor Division
Intel Corp.
Would this be my beloved Nehalem? *drool*
Does/could cache size influence the actual cores (TDP/heat dissipation...)?
Guess my real question is whether the cache is 'fed' into the cores, or actually searched by the cores?
(Sorry if this is a newb question but I am a complete newb and looking for oppurtunities to learn things and the interaction between cache and core on die is something I am curious about.)
Guess my real question is whether the cache is 'fed' into the cores, or actually searched by the cores?
(Sorry if this is a newb question but I am a complete newb and looking for oppurtunities to learn things and the interaction between cache and core on die is something I am curious about.)
The processor pulls information from and drops information to L1 cache constantly. L2 is basically overflow L1 and in some circumstances, shared by multiple cores. L3 is again essentially just more overflow and in some other(read different) cases is shared between multiple cores when the L2 is not. Cache plays a smaller role on Athlon 64's and phenoms because the memory controller is directly in the CPU so bleeding information off to system memory is much faster than having to put it throug an external memory controller.
I think you're all wrong. More cache can significantly increase the overall heat output, even though very little heat comes from the cache itself. Why? Because if you're missing constantly in a 2MB cache, but hitting constantly in a 4 or 8MB cache, the CPU cores are going to spend much less time in relatively low-power conditions waiting for data from memory, and more time doing higher-power computation. Even though the peak power doesn't increase much, the CPU spends much more time closer to the peak power.
but isnt the hit/miss application dependent? (I know the probability of success increases with size) If yes, then that line of argument will kinda make the OP question degenerate, as in the answer depends on the exact given scenario.
probably confining the analysis to a particular processor family and application environment might help
It's definitely application dependent. A simple rule of thumb would probably be "if the application gets faster with more cache, it runs hotter too".
No, he's talking about Itanium processors.
good point regarding core idling, but since the peak temperature in the critical logic blocks are still going to be the same, in regards to the original question of overclocking margin, i don't think there will be much difference, even across applications.
It is an interesting point that CTho9305 made. Basically if the cache is insufficient for the application then the CPU will be data starved and the average IPC will decline measurably, artificially capping the maximum heat generated.
But it begs the question though, are you overcloking just to get high clockspeed or are you overclocking to get high performance?
Get yourself a Netburst chip, disable the L2 cache, and clock her up to 6GHz of you want high clockspeed.
Get yourself the largest behemoth cache chip and clock her to her inherent thermal limits (allowing the cache to minimize IPC losses as CPU clocks outpace ram memory clocks) if you want to maximize performance.
But surely we all agree that ANYTHING which causes the average IPC for a processor to increase for any given application will also cause the average thermal output of the processor to increase which will in turn limit that maximum stable clockspeed within the systrem's TDP design envelope. (be it from more cache, more effective branch prediction, more effectively written code, etc)
cache doesnt use up that much power since its not switching all the time but it definitely uses some power.
look at the difference between say a core 2 cpu using a g0 core 4mb @ load and a m0 core. the m0 will use less power at load. at idle i believe the cache doesnt do much , and might even be shut off by power management (at least it does in mobile chips)
look at the difference between say a core 2 cpu using a g0 core 4mb @ load and a m0 core. the m0 will use less power at load. at idle i believe the cache doesnt do much , and might even be shut off by power management (at least it does in mobile chips)
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