Serial vs. Parallel

[Verdant]

I was reading the article on PCI-Express and was wondering if anyone can point me to an article... or respond to this...

How do serial buses obtain greater speeds than parallel buses?

I mean by dummy logic:
parallel devices use more lines == more bandwith?

and if it doesn't why can't a parallel configuration, be modified so that each line has about the same bandwith as each of the few lines in serial?

 

[AndyHui]

Not necessarily.

The problem with parallel buses is that as you increase the speed, you increase problems associated with clock skew. You need to guarantee that the signal in each line arrives on time, every time. This gets more difficult as you increase the speed. Parallel buses also require more traces. Again, placement and arrangement get more complex, and tolerances are reduced as speed increases.

With regards to speed, take a look at this analogy:

An 8-lane highway with a speed limit of 20mph represents a parallel link. The speeds must be lower, otherwise it would be really hard for each car in each lane to get from point A to point B at exactly the same time.

A 2-lane highway has a speed limit of 80mph, representing a serial link. The bandwidth for the serial link is the same, but speeds can be increased, as there are fewer lanes that need to arrive at the same time.

That's a really ham-fisted explanation, but I hope it gives you some sort of picture of the situation.

 

[Jeff7]

Originally posted by: AndyHui
Not necessarily.

The problem with parallel buses is that as you increase the speed, you increase problems associated with clock skew. You need to guarantee that the signal in each line arrives on time, every time. This gets more difficult as you increase the speed. Parallel buses also require more traces. Again, placement and arrangement get more complex, and tolerances are reduced as speed increases.

With regards to speed, take a look at this analogy:

An 8-lane highway with a speed limit of 20mph represents a parallel link. The speeds must be lower, otherwise it would be really hard for each car in each lane to get from point A to point B at exactly the same time.

A 2-lane highway has a speed limit of 80mph, representing a serial link. The bandwidth for the serial link is the same, but speeds can be increased, as there are fewer lanes that need to arrive at the same time.

That's a really ham-fisted explanation, but I hope it gives you some sort of picture of the situation.

And to add to that analogy - it's easier to merge with 2 lanes of traffic (assembling the data on a serial link) than it is with 8 lanes (parallel data link). If there's timing problems on one of those 8 lanes, you're looking at a serious pileup when a collision results.

 

[Confused]

Another way to look at it with Andy's explanation:

You (and every other car) are going 10 miles down this highway. There are 8 lanes, and you go at 20mph. It will take you 30 minutes to get 10 miles. 8 cars will do this in 30 minutes (saying that as one set of 8 cars get to the end, the next set of 8 start)

There are 2 lanes, going at 80mph. It will now take you 7.5 minutes to get down this road. In 30 minutes, however, 8 cars can still get down the road, (only 2 cars on the road at once) but each respective car gets there quicker.


I think i got that right

Confused

 

[Mday]

sidenote: the SATA roadmap has a future version of SATA with more lines\conductors for higher bandwidth. but it's been years since i saw it.

 

[Verdant]

thanks for all the anologies...

so the main problem with faster parallel is the problem with clock/signal synchronization?

i am just curious because PCI-Express supposedly can take us to the max transfer of copper, if another solution is not ready when we need more bandwith perhaps we will be fiddling with some sort of parallel solution again, perhaps one that does not require so much synchro... something like multiple "threads" (multiple seperate serial connections) or a bit arrival based bus (asynchronous between parallel lines)

of course i can see problems with the above; mutlple "threads" would require that the devices be able to generate more than one stream of data... and asynchronous would be difficult to group bits together to form the data

but i was just thinking out loud...

 

[Sunner]

Note that PCI-X is NOT PCI Express, it makes sense that the short version of PCI Express would be PCI-X, but that's not the case.

PCI-X is a backwards compatible extension of PCI 2.2, with speeds up to 133 MHz on a 64 bit bus, giving you roughly 1 GB/Sec of bandwidth.

 

[Verdant]

Yes, i know =( it was a automatic thing...

 

[AndyHui]

Verdant: look at the part explaining PCI Express lanes in my article.