Semimd: Deep Inside Intel (An Interview with Mark Bohr)

[cbn]

C.B., have you seen the latest on non-volatile MRAM?

Some info I found on Everspin. Apparently this is a low latency form of non-volatile memory that the company has arranged into the form of a DIMM (Sporting DDR3 speeds on the 90nm process.)

http://www.extremetech.com/computin...ic-ram-thats-500-times-faster-than-nand-flash

Notice the density difference. I am assuming this is comparing equivalent die sizes on the same process (but this should be verified and checked out).

http://semiaccurate.com/2012/11/16/everspin-makes-st-mram-a-reality/ (Good article. Mentions the 16x density increase possible when switching from 90nm process to 22/20nm process.)

http://www.computerworld.com/s/arti...ST_MRAM_memory_with_500X_performance_of_flash (Mentions Phase change and Memristor as other forms of Non-volatile memory on page 2 of the article.)

 

[Idontcare]

Some info I found on Everspin. Apparently this is a low latency form of non-volatile memory that the company has arranged into the form of a DIMM (Sporting DDR3 speeds on the 90nm process.)

Between ST-MRAM, FeRAM, and PRAM there are plenty of viable candidates to replace NAND if NAND should reach its scaling limits.

These boutique alternatives will always carry a price-premium as well as lag in terms of density because of the very fact that they are not in high volume manufacturing the likes of NAND and DRAM.

If they should ever come to receive the kinds of R&D attention and R&D dollars that NAND or DRAM see now then you can be assured the densities will dramatically improve and costs will fall just as dramatically.

What is awesome is that both the researchers and the consumers have a long future ahead of themselves of ever cooler stuff coming along in the arena of memory and storage :thumbsup:

 

[cbn]

Thanks IDC :thumbsup:

I also found information on 3D NAND here.

The discussion about NAND Litho caught my eye:

The increasing emphasis on 3D NAND comes as the cost of advancing planar 2D NAND to the next technology node — lithography in particular — may be prohibitive. 3D NAND could come in with a 55nm half pitch, possible using a dry lithography toolset.

Enticed by a shift from a lithography capital intensive 2D flow to a deposition and etch intensive approach, the major equipment vendors are paying close attention to 3D NAND equipment development.

Rather than adopt 16nm technology with multi-level-cell (MLC) NAND, memory vendors could turn to 55nm technology with 32 pairs of bit cells. “That will give the 3D NAND vendors a huge cost advantage. With that we will start to see a massive conversion to solid-state disk drives,” Archer said at SEMICON West.

Some more information regarding etching equipment for 3D NAND :

http://www.extremetech.com/computin...-vertical-3d-transistors-higher-capacity-ssds

Applied Materials has taken the wraps off a new etching system meant to turn vertically stacked, three-dimensional transistors from lab experiment

it can also be used to extend the lifespan of older process geometries by allowing manufacturers to build 3D NAND on 40-50nm processes. While such structures would still be larger than the equivalent chips built on 30-20nm tech, the tremendous efficiency gain from going vertical will more than offset the difference.

Assuming the 3D NAND started off at 55nm and progressed to 40nm, 28nm, 20nm that would be an 8x increase in density before makers would need consider 1x nm node 3D NAND vs. some of the other non-volatile memory techs you mentioned in your post.

Using a 2 year node cadence, that could postpone the need for quad patterning 193nm immersion or EUV by another 6 years.....assuming 55nm was indeed a viable starting point for 3D NAND.

EDIT: http://www.monolithic3d.com/2/post/2012/10/3d-nand-opens-the-door-for-monolithic-3d.html

With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition.

 

[Idontcare]

The horizontal channel approach for 3D NAND is killer (in a good way) because they can literally scale that up for decades to come if they wanted.

The downside is that the cost per chip is not reducing at that point. Consumers can get higher and higher density NAND but only with higher and higher prices.

Horizontal channels key to ultra-small 3D NAND