Semi-accurate has never been fully accurate hence the name. Burying it behind such a massive paywall enables them to stir up the hype without the need to deliver the meat. Those silly 5 investors won't share that 'knowledge' or make a dent in the stock market.
FWIW people speculating about skipping 10nm for 7nm clearly have no clue about the consequences and the ambitious specifications of 7nm. It's more dense then TSMC's 3nm process based on what is known right now about both processes.
If you can't jump 5ft you won't solve that by jumping 10ft.
What is likely at play here is Intel relaxing the m2 pitch from 36 to 40 or the m1/2 from 40/36 to both 44 to avoid the quad patterning of those two metal pitches. Depending on what their double patterning can handle it will either be 40 or 44nm. TSMC can handle 40 on their 7nm process but it's really unclear why Intel went with 36 in the first place.
Charlie sells that as 'dropping 10nm' which is simply hyperbole from an attention whore.
Agreed. People do not understand that processes can take 3-5 years in development before reaching the light of day, and even then they may not make it to see the light. Look at TSMCs scrapping of different nodes back around the 32nm/28nm timeline. TSMC has created a new process to have partners actively involved in the development of a process node in hopes to shrink the time to market with a new node or process refinement to 18 months. Very ambitious in my opinion. But no one is above the laws of physics, and trying to find ways to make a chip takes time, especially with the issues ahead. I will mention some of those issues in responses to others below.
There was a tweet by Intel which they stated that they HAVE NOT killed off their 10nm process. BUT what someone else said that it doesn't necessarily mean they are going to 7nm right away. Perhaps they could just be jumping to 10nm PLUS [10nm+] instead?
In light of development to implementation and Intel's current timeline suggesting introduction at 2021 or 2022, I find it dubious to pull the timeline in to 2020 even for risk production. Now, everyone is forgetting Intel said Ice Lake is coming next holidays, not cannon lake which is skylake at 10nm. They are skipping to introduce the new uarch and the 10nm+ process if that is to be considered an unchanged roadmap. What 10nm+ is, we do not know other than Intel mentioning in their own slides that the transistor performance (not separating out frequency or IPC) would be slightly less than 14nm++, while stating 10nm would be 25% more performance than 14nm (Intel press day March 29, 2017, IIRC). So, they will likely have a 10nm process of some sort, or some process more dense than 14nm, to present, but we really do not have a clue what it will look like or the performance to expect from it.
Now, on the points made about the article a couple weeks ago that yields are improving and production may have moved up by 6 weeks (half a quarter), Intel now reaffirming holiday 2019 and this report suggests that what was promising may not have panned out for some reason or another. Or they may be adopting another team's idea on how to get the density, but with a different set of tweaks to the process, which was less preferred than the last set of tweaks, but is better than scrapping the node all together. Hard to tell without what is behind the paywall.
Some claim its due to cobalt, some claim its the difficulty due to going above quad patterning.
My verdict?: It's all speculation until its actual.
Why speculate when you have hard data?
https://fuse.wikichip.org/news/1371...ghts-reports-on-the-i3-8121u-finds-ruthenium/
Tech Insights already opened the chip and analyzed it. And yes, its using 10nm technology.
"As far as cell size is concerned, there are no surprises. TechInsights silicon measurements matches Intel’s own IEDM paper."
"Techinsights has confirmed Intel is using contact-on-active gate (COAG)."
"For the three lowest layers (poly, metal 0, and metal 1), Intel introduced Cobalt and Tungsten."
They might have changed the cobalt gating too so maybe that's a definite cancellation of their original process in his eyes.
So, as you mentioned, it may be cobalt. As some have espoused, Intel is working on the problems of using Cobalt and transitioning to expensive other materials intended to help deal with the problems of quantum tunneling and electron "bleeding." While they work on this, other fabs, such as TSMC and Samsung, have focused on the introduction of EUV lithography, starting with the lowest layers for Samsung and eventually moving to the entire stack next year and TSMC hoping to have EUV in risk production on 7nm+ by 1H next year (likely Q2). Intel may not introduce EUV until 7nm, expected in 2021 back in August. (
https://www.eetimes.com/document.asp?doc_id=1333657).
We will need to do both as we quickly approach the issues related to node shrinks moving forward. Which is the best, focusing on the materials science side or on the lithography to reduce patterning defects and costs associated with quad patterning? Time will tell. But, Intel was burned on the promises of EUV being ready since 2015, a large reason that we are now sitting here, years later, with no 10nm chips from Intel.
Those issues with EUV still have not been resolved fully, such as mask problems with deformation, pellicles, etc. In fact, Samsung is moving use forward without some of that equipment, and TSMC is trying to do the same. They are pushing forward to make use of the EUV equipment while hounding the companies providing the equipment. But, they came to this point literally years after Intel was banking on its use in production, so Intel moving to the materials side, something not being done in manufacturing at the other fabs this early, instead them waiting for 5nm or 3nm to introduce cobalt, ruthenium, or other similar materials makes sense.
We also must remember that Intel's 7nm and the 5nm or 3nm processes at other fabs spells the end of finFETs as currently envisioned, instead potentially moving to nanowire and nanosheet Gate All Around transistors, which introduce their own difficulties in implementation.
Also, Intel may be choosing to less aggressively target pitch, as mentioned by Spartak (I agree with this), could be using cobalt less for contact or linings, etc. Time will tell.