Sandy Bridge Cache

[Edrick]

Hello,

I have been reading everything I can possibly find on this subject. And I have been finding conflicting information throughout the web. I realize that it is still early, but I hear Intel have these already speced out.

My question is what are going to be the cache sizes and latency for the Sandy Bridge CPUs (both mainstream and performance)

I have heard anywhere from 256k - 512k - 1m for the L2 with ranging latencies from 8 to 10 clocks.

As for L3 I am hearing anywhere from 1.5m to 2.5m per core with latencies ranging from 25 to 33 clocks.

Even on the L1, I heard speculation of an increase from 32+32 to 64+64, but I do not think Intel would do that. But the latency is supposed to drop back down to 3 clocks (from 4 on nehalem).

I also read something (if my memory is correct) that it will also include a new dedicated 8k cache for AVX instructions. I just can not find that article again.

Any info would be great.
Thanks.

 

[aigomorla]

Sandy bridge from what i heard isnt finalized yet.

So your not gonna get accurate info until at least testing samples are distributed.

 

[alyarb]

A0 silicon for the mainstream sandy bridge taped out over a year ago and was covered by techpowerup. they still have the only (crap) die photo of the mainstream variant. A1 silicon was demoed that fall during IDF. the size and speed of the caches of this variant are likely no longer open for discussion. Perhaps the more ambitious 8-12 core members that are farther down the pipeline are more up in the air. whatever intel is going to launch soonest (it might be the mainstream part first), you can be certain not only that the specs are closed, but that the masks exist and aren't going to change (or there would be some serious reluctance to overcome in making a change this late). sandy is really more than just one CPU though, and the 4-core socket 1155 part with the cache-connected IGP is the only variant people have any info on.

 

[IntelUser2000]

*snip*

I also read something (if my memory is correct) that it will also include a new dedicated 8k cache for AVX instructions. I just can not find that article again.

Any info would be great.
Thanks.

There's no dedicated AVX cache, that's kinda ridiculous. Enhancing AVX performance that way won't help general computing a whole lot. Well, the source you read from or yourself might have got confused with the LSD(Loop Stream Detector) buffer being greatly enlarged. LSD, has its roots back to the Trace Cache days of the Pentium 4.

The leaked die shot also has strange L3 cache configuration. On Bloomfield and Gulftown you'll notice there are 4 groups of 2 1MB blocks. On Sandy Bridge, the 3 groups of 2 are just like Bloomfield, but the 1 group of 2 is not together, but seperate. I suspect because cache structure is being changed.

I suspect the only reason it looks complicated is because they are keeping its secrets well. Nehalem brought mere 10% in per core performance, but its focus was in multi-threading and memory bandwidth. I'd think Sandy Bridge would bring more balanced performance increases for general computing.