[SA] Intel guts 10nm to get it out the door

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Spartak

Senior member
Jul 4, 2015
298
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#51
EUV equipment is not even fully available today, so it wasn't remotely under consideration when Intel first started trying to get it's "10nm" process running. Intel didn't make a choice, because there was no choice to make.

In that Kanter interview I linked above, he says that everyone is doing multi-Patterning without EUV for the first attempt at the next jump (Intel 10nm/TSMC 7nm/GF 7nm) though IIRC TSMC and/or GF stated they will add EUV later to their 7nm process.

The problem is that EUV has been the unicorn that will save them for years, but the equipment is still not quite ready for EUV at this time, so it keeps getting pushed out.
What he said was wrong on both accounts. By saying Multi-patterning he's putting a smoke screen around the reported/rumored issue of quad patterning the metal layers which only Intel is doing. The smallest 7nm metal pitch for GF&TSMC is 40nm, so can be done with double patterning. The smallest 7nm metal pitch for Samsung is 36nm, like Intel. However Samsung will be using EUV. So I guess the unicorn got real as well.

The 'always around the corner' trope used by David is getting really old as well. Development started in the late 90ies, which was decidedly long term. It had huge delays but if it was an easy nut to crack then why is ASML the only company developing the technology?

That interview with David Kanter was incredibly boring and the guy had nothing but wrong tropes to add to the subject to be honoust. Camouflaging the issue instead of pointing it out.

Frankly my money is on Intel relaxing the n1 pitch to 40nm, but who knows maybe they found a way to make quad patterning work for them.

edit: corrected for clarity
 
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PeterScott

Platinum Member
Jul 7, 2017
2,605
227
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#52
What he said was wrong on both accounts. By saying Multi-patterning he's putting a smoke screen around the specific issue of quad patterning which only Intel is doing.
It has been reported in multiple locations that GF/TSMC are starting off 7nm with DUV and quad patterning:

https://www.zdnet.com/article/iedm-2017-globalfoundries-announces-7nm-chipmaking-process/
Like Intel, GlobalFoundries will use self-aligned quad patterning (SAQP) to fabricate the fins,

http://semimd.com/blog/tag/7nm/
TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”
 

Spartak

Senior member
Jul 4, 2015
298
137
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#53
we were discussing the issues the metal contacts have that appear to be related to SAQP...not the fins, but point granted, technically everone uses quad patterning.
 

jpiniero

Diamond Member
Oct 1, 2010
6,570
315
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#54
TSMC's 7+ with some layers using EUV is supposed to go HVM some time in 2019 and 5 with full EUV in 2020. I guess we will see if that happens.

Still appears that Intel will be last of the four to use EUV in any capacity.
 

PeterScott

Platinum Member
Jul 7, 2017
2,605
227
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#55
we were discussing the issues the metal contacts have that appear to be related to SAQP...not the fins, but point granted, technically everone uses quad patterning.
Where did you read Intel's problem was with metal contacts? GF is starting EUV with metal contacts, not because it is critical, but because it is easiest.
 

Spartak

Senior member
Jul 4, 2015
298
137
116
#56
this has been the story from the start, how the rumour started on Twitter I think? its the m0/m1 pitch that are being done through SAQP. Then there is the use of cobalt that has its own issues. Whether there is a relation between both issues is unclear but likely two separate issues.

I'd like to hear where you got that the metal contacts are the "easiest"? AFAIK the metal contacts are the most critical, so this is where you'd want to start using EUV.
 
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PeterScott

Platinum Member
Jul 7, 2017
2,605
227
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#57
this has been the story from the start, how the rumour started on Twitter I think? its the m0/m1 pitch that are being done through SAQP. Then there is the use of cobalt that has its own issues. Whether there is a relation between both issues is unclear but likely two separate issues.

I'd like to hear where you got that the metal contacts are the "easiest"? AFAIK the metal contacts are the most critical, so this is where you'd want to start using EUV.
I have heard SAQP difficulties all along, but nothing about contacts.

As far as contacts being easier. They don't require an EUV pellicle layer that is needed for most features. The pellicle layer for EUV is still not at an adequate state.

https://www.extremetech.com/computing/263286-sitting-globalfoundries-talk-7nm-euv
GlobalFoundries’ solution? Use EUV for contacts and vias while a pellicle solution is being worked on. Since you don’t need one for these areas of the chip, you can increase EUV throughput and reduce cycle time. Going forward, GF will adopt EUV for more critical mask layers. The CTO and SVP of Worldwide R&D at GF, Dr. Gary Patton, has suggested EUV is a functional requirement for 5nm or below.
 

PeterScott

Platinum Member
Jul 7, 2017
2,605
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#59
I have read many articles about it at this point including the semiwiki ones. Most of it is speculative beyond what Intel themselves have admitted. A lot of made about that one Metal Layer being 36nm for Intel and 40nm for GF. Or simply looking at any difference between Intel and the competition and assuming anything Intel is doing different, is wrong. While those differences are easy targets, they aren't necessarily correct.

My speculation is a lot of the earlier delay was due to Intel pushing the limits of technique like SAQP first, when the equipment may not have been as good. The Fabs don't build the process equipment, so they can't push beyond what ASML (or others) have the equipment ready to do. ASML will have been improving the SAQP equipment all along so those who started later, likely get to skip early issues.

The baffling part is why Intel was so public about feature sizes without having some good test work already completed to show they were on track. Like that 36nm metal layers. Shouldn't they have tested it before making part of their process on the public record?

I doubt we will ever get the full story on how Intel made such a public mess of 10nm.
 

witeken

Diamond Member
Dec 25, 2013
3,868
11
106
#60
My speculation is a lot of the earlier delay was due to Intel pushing the limits of technique like SAQP first, when the equipment may not have been as good. The Fabs don't build the process equipment, so they can't push beyond what ASML (or others) have the equipment ready to do. ASML will have been improving the SAQP equipment all along so those who started later, likely get to skip early issues.
Incorrect. SAQP has to be developed in-house by the fabs. It uses standard equipment such as ASML's immersion lithography.
 


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