EUV equipment is not even fully available today, so it wasn't remotely under consideration when Intel first started trying to get it's "10nm" process running. Intel didn't make a choice, because there was no choice to make.
In that Kanter interview I linked above, he says that everyone is doing multi-Patterning without EUV for the first attempt at the next jump (Intel 10nm/TSMC 7nm/GF 7nm) though IIRC TSMC and/or GF stated they will add EUV later to their 7nm process.
The problem is that EUV has been the unicorn that will save them for years, but the equipment is still not quite ready for EUV at this time, so it keeps getting pushed out.
What he said was wrong on both accounts. By saying Multi-patterning he's putting a smoke screen around the reported/rumored issue of quad patterning the metal layers which only Intel is doing. The smallest 7nm metal pitch for GF&TSMC is 40nm, so can be done with double patterning. The smallest 7nm metal pitch for Samsung is 36nm, like Intel. However Samsung will be using EUV. So I guess the unicorn got real as well.
The 'always around the corner' trope used by David is getting really old as well. Development started in the late 90ies, which was decidedly long term. It had huge delays but if it was an easy nut to crack then why is ASML the only company developing the technology?
That interview with David Kanter was incredibly boring and the guy had nothing but wrong tropes to add to the subject to be honoust. Camouflaging the issue instead of pointing it out.
Frankly my money is on Intel relaxing the n1 pitch to 40nm, but who knows maybe they found a way to make quad patterning work for them.
edit: corrected for clarity