Ryzen: Strictly technical

[The Stilt]

Regarding Excavator- can you disable CMT in BIOS?
Regarding Himeno and Nbody- is it likely another size of these BM would give a very different result?
3D Euler seem do be hard to predict- Caselab and CFD are very different.
3D Euler tested at techreport.com is even worse for Ryzen.

You can, by selecting "single core per compute unit" (standard AGESA downcore).
Alternatively you can set a mask of 0xA to the downcore PCI register (check BKDG). That will disabled the slave cores within the CU.

Neither Himeno or NBody results change when the grid-size (Himeno) or body count (NBody) is changed.

Techreport didn't use patched version of Caselab Euler3D, like I did.
The program is extremely old and has been compiled with a ICL version of that ERA (pre court ruling), meaning it features a hostile CPU vendor dispatcher.
Unless the dispatcher is removed through patching, it significantly degrades the performance on AMD CPUs. The difference can be as high as 30% (SSE vs. SSE2, IIRC).

 

[CatMerc]

R7 1700 SHOULD have 3.05GHz ACXFRC (due being non-X), however there is indication that it's not necessarily the case.
Unfortunately I don't have the data available, to check it right now.



Based on my own tests, the average performance benefit from higher than 2400MHz DRAM (i.e. 1200MHz DFICLK) is very marginal in 2D, even with 8C/16T config. Will smaller core count even 2133MHz is fine.

There are various interfaces / fabrics inside Zeppelin and their functionality and relations are not fully known at the moment. So eventhou the data fabric operates at half the effective MEMCLK, that doesn't necessarily mean that the inter-CCX connections are operating at the speculated width and speed. There are parts of the fabric which are 256-bit wide for example.

Moving to another node (such as 16nm FF+) is really a nobrainer, if it yields in <10% increased Fmax. Porting the design will be extremely expensive, however not NEARLY as expensive as trying to increase IPC of the µarch itself. The results in terms of the performance are always guaranteed when increasing the frequency on existing design, while that's not the case on a modified µarch featuring higher IPC. The modified µarch may necessarily not be able to reach same speeds as the old one did, so the actual performance may remain the same or even degrade.

Depending on the performance characteristics, they might move to 14nm LPU. Probably easier to handle from the WSA's point of view.

 

[The Stilt]

So does it makes more sense cost and time wise for AMD to use Samsung 14nm LPU or totally port their design to TSMC 16 nm FF+
TSMC's 16 FF+ seems to clock higher than samsung's 14nm LPP/LPC but isn't LPU supposed to catch up here?
Also Glo Fo will skip 10nm right?

14nm LPP is perfectly fine (and potentially even the optimal choice) for low clocked, high core count server parts (such as Naples).
The consumer parts definitely need a higher Fmax capability and most likely 16nm FF+ could provide that.

The issue with the newer Samsung process variant is that they are currently not available, and are not proven in practice like the 16nm FF+ is.

 

[CatMerc]

14nm LPP is perfectly fine (and potentially even the optimal choice) for low clocked, high core count server parts (such as Naples).
The consumer parts definitely need a higher Fmax capability and most likely 16nm FF+ could provide that.

The issue with the newer Samsung process variant is that they are currently not available, and are not proven in practice like the 16nm FF+ is.

But Raven Ridge as a laptop part would also benefit greatly from LPP's power characteristics.

 

[Kromaatikse]

Re Himeno, I actually took the time to look at the code yesterday. It was clearly written by a physical scientist, not a software engineer, which is a polite way of saying that it is RIDICULOUSLY inefficient code. GCC and Clang actually do a good job of moving most of the inefficiency out of the innermost loop, but at Phoronix' test size, that gives only 64 iterations at reasonable FPU-op density before it has to wade back into a mire of integer multiplies and register spilling to set up pointers for the next row.

If it wouldn't invalidate the benchmark, I'd happily rewrite it to use a much more efficient representation of the data it's working on. As it stands, it cannot actually make effective use of AVX2, because the compiler has no clue how to vectorise something this badly written. Turning on -mavx2, as Phoronix does, only results in a small matrix-copy operation using the AVX registers.

With that said, I'm still at a loss as to why it's consistently slow on AMD and faster on Intel. After all, Phoronix compiles that benchmark from scratch each run.

 

[Wolfgang Weidner]

Ryzen directly connects audio and M.2 ( edit: and USB ) beside RAM and PCIe , so will we see system boards without extra I/O chipset like B350? For mobile platforms maybe?

 

[The Stilt]

@The Stilt,
so far you seem to be only one to get Win7 running, could you write a few words how you managed to do this. My own tries with my existing installation or with the win7 installation DVD (USB & SATA drive) had not much success, win7 always hangs during booting.

Could you please tell how you managed to get win7 running?

Copy dism.exe, boot.wim & install.wim (sources directory) files from the Windows 7 ISO image to your hard-drive.
Download the USB driver for Ryzen: https://1drv.ms/u/s!Ag6oE4SOsCmDhGIQJdHdaXC-_w-C
Extract the package to the same directory as DISM is located.
Enter the folders containing the individual driver files and check that there is not "Unblock" button visible. If there is, you need to manually toggle it for each and every file.

- "DISM /mount-wim /wimfile:boot.wim /index:2 /mountdir:x:\xxx" (x:\xxx = a temporary path of your choice, make sure to have ~20GB of space available for install.wim).
- "DISM /image:x:\xxx /add-driver /driver:Ryzen_USB_W764\ /recurse /forceunsigned"
- "DISM /unmount-wim /mountdir:x:\xxx /commit"

Windows 7 install.wim files contain four different OS variants, regardless of the officially stated edition of the media you have (Home, Professional, Ultimate).
The index order within the install.wim is always the same, regardless of the edition: Index 1 = Home Basic, Index 2 = Home Premium, Index 3 = Professional, Index 4 = Ultimate.

So if your media is for Professional edition, you need to make the changes to Index 3. If it is a Ultimate media, then make the changes to Index 4, etc.

- "DISM /mount-wim /wimfile:install.wim /index:x /mountdir:x:\xxx" (x:\xxx = a temporary path of your choice, make sure to have ~20GB of space available for install.wim).
- "DISM /image:x:\xxx /add-driver /driver:Ryzen_USB_W764\ /recurse /forceunsigned"
- "DISM /unmount-wim /mountdir:x:\xxx /commit"

After you have added the drivers to both of the WIMs, you can install Windows 7 from a USB drive and using USB keyboard and mouse.
Make sure that you don't use USB ports provided by a 3rd party manufacturer (other than ASMedia), as there are still no drivers for those in the media.
After the installation, install the Relive chipset driver pack for Windows 7 (available at AMD.com).

 

[deadhand]

But Raven Ridge as a laptop part would also benefit greatly from LPP's power characteristics.

The idle power characteristics of Ryzen appear to be fantastic. I could imagine a Ryzen APU being a great part in a laptop.

 

[malitze]

I guess the HWinfo temperatures are correct at least. But my Crosshair just bricked, so any further testing has to wait. This could be a serious bug btw. I'm not the only one it seems. Edit: And this one seems to be similar as well.

I probably went through the same dilemma, already gave up on the board except one desperate attempt with this BIOS. Now booting fine again. Might be worth a try.

 

[PG]

I got Win7 installed, but I didn't do anything too fancy like slip streaming drivers to get it done. The key for me was having a PS2 keyboard and then having a PS2 mouse adapter. Well, I used a win7 DVD in an optical drive. That is also necessary.

My board is the Asus Prime B350-Plus. It only has one PS2 port so I had to do some shenanigans to get things done.

First have the DVD in the drive and the PS2 keyboard plugged in. Don't bother with a USB mouse because it won't work anyway. Boot from the DVD and you can do what you need with the keyboard to get windows installed. You have to remember certain keyboard tricks like using tab and arrow keys. Nothing hard, but most don't use these on a daily basis probably when you normally have a working mouse.
Do not put in a windows password. Leave that blank. This is critical for later.

After windows is installed I put the Asus driver DVD in. You get a popup about what to do and you can hit enter and get to the main menu, but there I was stuck. I couldn't get any keyboard tricks to work to move from the initial menu area to the driver area. Arrow keys and tab didn't do squat. I had to shut down and think about things a bit.

Now unplug the PS2 keyboard. Get the mouse PS2 to USB adapter. You plug that in the PS2 port and plug the mouse into it. The keyboard won't be plugged in or used for the next step.

Boot up, mouse only, and if you don't have a password it goes direct to the desktop. Now with the mouse you can navigate the driver disk menu and get the drivers installed. After installing and a reboot or two you are set. You can then put the keyboard and mouse both in how you want and they will work.

 

[gupsterg]

R7 1700 SHOULD have 3.05GHz ACXFRC (due being non-X), however there is indication that it's not necessarily the case.
Unfortunately I don't have the data available, to check it right now.

Thank you , waiting on mobo at present, CPU/RAM at hand only .

Another question if you can help with, I had seen this:-

AMD Ryzen™ processors do not use pre-programmed VID tables.
1. Therefore, there is no fixed Vcore when the CPU runs in its out-of-box condition.
2. Default Vcore will vary depending on workload and will range from 1.2-1.3625V.
3. Overclocking an AMD Ryzen™ processor will snap the voltage to 1.3625V, but this value can be changed.

I'm collecting data for Ryzen and would like to have data showing VID/VCORE for a CPU for comparison with another at "out-of-box" setup. Is it best to assess default VID/VCORE for a CPU whilst in UEFI monitoring?

 

[Encrypted11]

I was looking for more IO testing than the limited info published by the tech press.

I appreciate the reply while being honest and upfront. Your article is a good read nonetheless. (Been reading your previous work like EMBD etc as well)

Unfortunately I don't have the equipment to do that.

 

[The Stilt]

Thank you , waiting on mobo at present, CPU/RAM at hand only .

Another question if you can help with, I had seen this:-



I'm collecting data for Ryzen and would like to have data showing VID/VCORE for a CPU for comparison with another at "out-of-box" setup. Is it best to assess default VID/VCORE for a CPU whilst in UEFI monitoring?

The default VID (ceiling) for the base state (P0) can be read from MSR 0xC0010064.
However since the SMU adds a variable negative offset to that value, and the offset varies depending on temperature, load and silicon characteristics...
There is really no way for the end-users to know their actual default voltage. If the user has both the knowledge and a compatible motherboard (IR controller), then the VID driven by the SMU can be read from the controller registers.
Monitoring the actual voltage through software (CPU-Z, HWInfo, etc) doesn't produce comparable information to determine the differences between specimens.

 

[wiak]

coreinfo for

Spoiler: FX-8350

AMD FX(tm)-8350 Eight-Core Processor
AMD64 Family 21 Model 2 Stepping 0, AuthenticAMD
Microcode signature: 06000822
HTT * Multicore
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM * Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode

SMX - Supports Intel trusted execution
SKINIT * Supports AMD SKINIT

NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS - Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access

FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT * Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a * Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2

AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction

CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions

DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR - Supports disabling task priority messages

EIST - Supports Enhanced Intel Speedstep
ACPI - Implements MSR for power management
TM - Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC

CNXT-ID - L1 data cache mode adaptive or BIOS

MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE - Supports use of FERR#/PBE# pin

PSN - Implements 96-bit processor serial number

PREFETCHW * Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended).

Logical to Physical Processor Map:
**------ Physical Processor 0 (Hyperthreaded)
--**---- Physical Processor 1 (Hyperthreaded)
----**-- Physical Processor 2 (Hyperthreaded)
------** Physical Processor 3 (Hyperthreaded)

Logical Processor to Socket Map:
******** Socket 0

Logical Processor to NUMA Node Map:
******** NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*------- Data Cache 0, Level 1, 16 KB, Assoc 4, LineSize 64
**------ Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
**------ Unified Cache 0, Level 2, 2 MB, Assoc 16, LineSize 64
******** Unified Cache 1, Level 3, 8 MB, Assoc 64, LineSize 64
-*------ Data Cache 1, Level 1, 16 KB, Assoc 4, LineSize 64
--*----- Data Cache 2, Level 1, 16 KB, Assoc 4, LineSize 64
--**---- Instruction Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64
--**---- Unified Cache 2, Level 2, 2 MB, Assoc 16, LineSize 64
---*---- Data Cache 3, Level 1, 16 KB, Assoc 4, LineSize 64
----*--- Data Cache 4, Level 1, 16 KB, Assoc 4, LineSize 64
----**-- Instruction Cache 2, Level 1, 64 KB, Assoc 2, LineSize 64
----**-- Unified Cache 3, Level 2, 2 MB, Assoc 16, LineSize 64
-----*-- Data Cache 5, Level 1, 16 KB, Assoc 4, LineSize 64
------*- Data Cache 6, Level 1, 16 KB, Assoc 4, LineSize 64
------** Instruction Cache 3, Level 1, 64 KB, Assoc 2, LineSize 64
------** Unified Cache 4, Level 2, 2 MB, Assoc 16, LineSize 64
-------* Data Cache 7, Level 1, 16 KB, Assoc 4, LineSize 64

Logical Processor to Group Map:
******** Group 0

 

[looncraz]

The Infinity fabric is at 512 Gbytes/s in Vega but unclear what latency.

The infinity fabric wouldn't need to operate at 512GiB/sec at all.

Each HBM stack is 1024 bits wide and that is split between eight 128-bit channels. That only requires 16GiB/sec of bandwidth on the infinity fabric for HBM1 - and 32GiB/sec for HBM2.

Vega can just use some multiplier for the infinity fabric frequency since we already know that it can eclipse 32GiB/sec in Ryzen - at less than 1.5Ghz, no less. To me, given Vega's rumored clock-speed of 1.5Ghz, I'd just lock the data fabric to the GPU clock.

 

[deadhand]

For anyone interested in the similarities to the PS4's core organization (2 quad core modules, like Ryzen):

http://www.dualshockers.com/2014/03...l-and-how-they-can-make-them-run-really-fast/

 

[looncraz]

Moving to another node (such as 16nm FF+) is really a nobrainer, if it yields in <10% increased Fmax. Porting the design will be extremely expensive, however not NEARLY as expensive as trying to increase IPC of the µarch itself. The results in terms of the performance are always guaranteed when increasing the frequency on existing design, while that's not the case on a modified µarch featuring higher IPC. The modified µarch may necessarily not be able to reach same speeds as the old one did, so the actual performance may remain the same or even degrade.

It would take AMD over a year longer to move to 16nm and would look bad from a marketing perspective (because people are dumb). I think AMD can squeeze out the same performance from 14nm LPP with some more refinements. They have ~4Ghz already - with about 400MHz added in just two steppings. It's a matter of identifying and refining the critical pathways.

If AMD were to consider another process for Zenver2, my bet would be on 7nm. It's preparing to enter sample production later this year, risk production early next year, and ramp through 2018.

However, I imagine Zenver2 is planned for 14nm LPP or a close relative - otherwise AMD might be spending 24+ months getting out an update, which would be a disaster as Intel will be on its 10nm node and have higher IPC, higher clocked, native six-core CPUs in the mainstream market. AMD needs to be able to respond quickly.

 

[Evil Azrael]

@The Stilt & PG thanks for the Information, got my existing Win7 Installation working again. Hope Google picks these posts up soon.
Maybe good to know is that the AMD Overdrive service BSODs during bootup. Deinstall AMD overdrive and everything should work.

(Another problem was a bad DIMM, this prevented booting anything at all)

 

[The Stilt]

It would take AMD over a year to move to 16nm and would look bad from a marketing perspective (because people are dumb). I think AMD can squeeze out the same performance from 14nm LPP with some more refinements. They have ~4Ghz already - with about 400MHz added in just two steppings. It's a matter of identifying and refining the critical pathways.

If AMD were to consider another process for Zenver2, my bet would be on 7nm. It's preparing to enter sample production later this year, risk production early next year, and ramp through 2018.

However, I imagine Zenver2 is planned for 14nm LPP or a close relative - otherwise AMD might be spending 24+ months getting out an update, which would be a disaster as Intel will be on its 10nm node and have higher IPC, higher clocked, native six-core CPUs in the mainstream market. AMD needs to be able to respond quickly.

Frankly I don't believe that the 14nm LPP will significatly improve any more. 14nm LPE, which is extremely closely related to LPP has been in mass production for 21 months now. Also the 14nm LPP itself has been in mass production for 15 months.
AMD most likely could tweak thing or two in the design in order to reach higher Fmax, however I fear that most of the tricks were already used in the final stepping of Zeppelin.

For the upcoming Zen iterations I would rather see AMD staying on a process, which has been fully tested in practice. Regardless if it means falling behind in the absolute node size. 16nm FF+ is extremely well proven and also 14nm HP (IBM) should be available at some point from GlobalFoundries. Moving immediately to a new 7nm node would be like taking a head dive into unknown waters, once more.

 

[looncraz]

@The Stilt

When you say 1/2 MEMCLK, you are saying that with DDR4-2400 the DFICLK is 1200MHz, right?

Not 600Mhz, which would actually be 1/2 of the real RAM clock, since DDR is double-pumped.

 

[The Stilt]

@The Stilt

When you say 1/2 MEMCLK, you are saying that with DDR4-2400 the DFICLK is 1200MHz, right?

Not 600Mhz, which would actually be 1/2 of the real RAM clock, since DDR is double-pumped.

Yes, half of the effective (2400MHz = 1200MHz).

 

[Insert_Nickname]

Any chance you can fill in the x.xGHz ACXFC for a R7 1700?

For example, for the 1700 SKU the clock configuration is following: 3.0GHz all core frequency (MACF), 3.7GHz single core frequency (MSCF), x.xGHz maximum all core XFR ceiling (ACXFRC) and 3.75GHz maximum single core XFR ceiling (SCXFRC).

Certainly. It is 3.2GHz.

I ran the draw call benchmark on my Ryzen 1800x (OC'd to 4ghz) and averaged 17 fps. I've been messing with this system for hours through numerous reboots, and at some point I was getting 14, but I'm pretty sure I was at 4ghz then as well. The BIOS for the Asus Crosshair is really not in a good state. My voltages have been screwy and I've given up on getting my 3200 ram working past 2666 for now.

The Crosshair BIOS (0702) is a mess with memory compatibility currently. But it is at least stable.

 

[looncraz]

Frankly I don't believe that the 14nm LPP will significatly improve any more. 14nm LPE, which is extremely closely related to LPP has been in mass production for 21 months now. Also the 14nm LPP itself has been in mass production for 15 months.
AMD most likely could tweak thing or two in the design in order to reach higher Fmax, however I fear that most of the tricks were already used in the final stepping of Zeppelin.

For the upcoming Zen iterations I would rather see AMD staying on a process, which has been fully tested in practice. Regardless if it means falling behind in the absolute node size. 16nm FF+ is extremely well proven and also 14nm HP (IBM) should be available at some point from GlobalFoundries. Moving immediately to a new 7nm node would be like taking a head dive into unknown waters, once more.

Precisely why I think AMD will stick with 14nm LPP or a very close cousin (maybe LPU, if they are actually using Samsung's fab in Austin). LPU has some 10% higher power, which should allow the same design to hit 4.2~4.4Ghz rather reliably. With higher IPC and other refinements, that would allow Zenevr2 to be competitive as Zenver3 is planned for 7nm in 2019 or 2020 - using a node that will have then been in use for 12 months.

Even with 14nm LPP I think there is some more headroom. AMD could refine their HDL and eek out some more hertz.

 

[Mockingbird]

Spoiler

AMD Ryzen: ZD3601BAM88F4_40/36_Y           
AMD64 Family 23 Model 1 Stepping 1, AuthenticAMD
HTT           *   Multicore
HYPERVISOR   -   Hypervisor is present
VMX           -   Supports Intel hardware-assisted virtualization
SVM           *   Supports AMD hardware-assisted virtualization
X64           *   Supports 64-bit mode

SMX           -   Supports Intel trusted execution
SKINIT       *   Supports AMD SKINIT

NX           *   Supports no-execute page protection
SMEP         *   Supports Supervisor Mode Execution Prevention
SMAP         *   Supports Supervisor Mode Access Prevention
PAGE1GB       *   Supports 1 GB large pages
PAE           *   Supports > 32-bit physical addresses
PAT           *   Supports Page Attribute Table
PSE           *   Supports 4 MB pages
PSE36         *   Supports > 32-bit address 4 MB pages
PGE           *   Supports global bit in page tables
SS           -   Supports bus snooping for cache operations
VME           *   Supports Virtual-8086 mode
RDWRFSGSBASE   *   Supports direct GS/FS base access

FPU           *   Implements i387 floating point instructions
MMX           *   Supports MMX instruction set
MMXEXT       *   Implements AMD MMX extensions
3DNOW         -   Supports 3DNow! instructions
3DNOWEXT      -   Supports 3DNow! extension instructions
SSE           *   Supports Streaming SIMD Extensions
SSE2         *   Supports Streaming SIMD Extensions 2
SSE3         *   Supports Streaming SIMD Extensions 3
SSSE3         *   Supports Supplemental SIMD Extensions 3
SSE4a         *   Supports Streaming SIMDR Extensions 4a
SSE4.1       *   Supports Streaming SIMD Extensions 4.1
SSE4.2       *   Supports Streaming SIMD Extensions 4.2

AES           *   Supports AES extensions
AVX           *   Supports AVX intruction extensions
FMA           *   Supports FMA extensions using YMM state
MSR           *   Implements RDMSR/WRMSR instructions
MTRR         *   Supports Memory Type Range Registers
XSAVE         *   Supports XSAVE/XRSTOR instructions
OSXSAVE       *   Supports XSETBV/XGETBV instructions
RDRAND       *   Supports RDRAND instruction
RDSEED       *   Supports RDSEED instruction

CMOV         *   Supports CMOVcc instruction
CLFSH         *   Supports CLFLUSH instruction
CX8           *   Supports compare and exchange 8-byte instructions
CX16         *   Supports CMPXCHG16B instruction
BMI1         *   Supports bit manipulation extensions 1
BMI2         *   Supports bit manipulation extensions 2
ADX           *   Supports ADCX/ADOX instructions
DCA           -   Supports prefetch from memory-mapped device
F16C         *   Supports half-precision instruction
FXSR         *   Supports FXSAVE/FXSTOR instructions
FFXSR         *   Supports optimized FXSAVE/FSRSTOR instruction
MONITOR       *   Supports MONITOR and MWAIT instructions
MOVBE         *   Supports MOVBE instruction
ERMSB         -   Supports Enhanced REP MOVSB/STOSB
PCLMULDQ      *   Supports PCLMULDQ instruction
POPCNT       *   Supports POPCNT instruction
LZCNT         *   Supports LZCNT instruction
SEP           *   Supports fast system call instructions
LAHF-SAHF    *   Supports LAHF/SAHF instructions in 64-bit mode
HLE           -   Supports Hardware Lock Elision instructions
RTM           -   Supports Restricted Transactional Memory instructions

DE           *   Supports I/O breakpoints including CR4.DE
DTES64       -   Can write history of 64-bit branch addresses
DS           -   Implements memory-resident debug buffer
DS-CPL       -   Supports Debug Store feature with CPL
PCID         -   Supports PCIDs and settable CR4.PCIDE
INVPCID       -   Supports INVPCID instruction
PDCM         -   Supports Performance Capabilities MSR
RDTSCP       *   Supports RDTSCP instruction
TSC           *   Supports RDTSC instruction
TSC-DEADLINE   -   Local APIC supports one-shot deadline timer
TSC-INVARIANT   *   TSC runs at constant rate
xTPR         -   Supports disabling task priority messages

EIST         -   Supports Enhanced Intel Speedstep
ACPI         -   Implements MSR for power management
TM           -   Implements thermal monitor circuitry
TM2           -   Implements Thermal Monitor 2 control
APIC         *   Implements software-accessible local APIC
x2APIC       -   Supports x2APIC

CNXT-ID       -   L1 data cache mode adaptive or BIOS

MCE           *   Supports Machine Check, INT18 and CR4.MCE
MCA           *   Implements Machine Check Architecture
PBE           -   Supports use of FERR#/PBE# pin

PSN           -   Implements 96-bit processor serial number

PREFETCHW    *   Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 8000001F (Extended).

Logical to Physical Processor Map:
**--------------  Physical Processor 0 (Hyperthreaded)
--**------------  Physical Processor 1 (Hyperthreaded)
----**----------  Physical Processor 2 (Hyperthreaded)
------**--------  Physical Processor 3 (Hyperthreaded)
--------**------  Physical Processor 4 (Hyperthreaded)
----------**----  Physical Processor 5 (Hyperthreaded)
------------**--  Physical Processor 6 (Hyperthreaded)
--------------**  Physical Processor 7 (Hyperthreaded)

Logical Processor to Socket Map:
****************  Socket 0

Logical Processor to NUMA Node Map:
****************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*---------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*---------------  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
*---------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
*---------------  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
-*--------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*--------------  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
-*--------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
-*--------------  Unified Cache       3, Level 3,   16 MB, Assoc  16, LineSize  64
--*-------------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
--*-------------  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
--*-------------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
--*-------------  Unified Cache       5, Level 3,   16 MB, Assoc  16, LineSize  64
---*------------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
---*------------  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
---*------------  Unified Cache       6, Level 2,  512 KB, Assoc   8, LineSize  64
---*------------  Unified Cache       7, Level 3,   16 MB, Assoc  16, LineSize  64
----*-----------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
----*-----------  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
----*-----------  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
----*-----------  Unified Cache       9, Level 3,   16 MB, Assoc  16, LineSize  64
-----*----------  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
-----*----------  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
-----*----------  Unified Cache      10, Level 2,  512 KB, Assoc   8, LineSize  64
-----*----------  Unified Cache      11, Level 3,   16 MB, Assoc  16, LineSize  64
------*---------  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------*---------  Instruction Cache   6, Level 1,   64 KB, Assoc   4, LineSize  64
------*---------  Unified Cache      12, Level 2,  512 KB, Assoc   8, LineSize  64
------*---------  Unified Cache      13, Level 3,   16 MB, Assoc  16, LineSize  64
-------*--------  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
-------*--------  Instruction Cache   7, Level 1,   64 KB, Assoc   4, LineSize  64
-------*--------  Unified Cache      14, Level 2,  512 KB, Assoc   8, LineSize  64
-------*--------  Unified Cache      15, Level 3,   16 MB, Assoc  16, LineSize  64
--------*-------  Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
--------*-------  Instruction Cache   8, Level 1,   64 KB, Assoc   4, LineSize  64
--------*-------  Unified Cache      16, Level 2,  512 KB, Assoc   8, LineSize  64
--------*-------  Unified Cache      17, Level 3,   16 MB, Assoc  16, LineSize  64
---------*------  Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
---------*------  Instruction Cache   9, Level 1,   64 KB, Assoc   4, LineSize  64
---------*------  Unified Cache      18, Level 2,  512 KB, Assoc   8, LineSize  64
---------*------  Unified Cache      19, Level 3,   16 MB, Assoc  16, LineSize  64
----------*-----  Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
----------*-----  Instruction Cache  10, Level 1,   64 KB, Assoc   4, LineSize  64
----------*-----  Unified Cache      20, Level 2,  512 KB, Assoc   8, LineSize  64
----------*-----  Unified Cache      21, Level 3,   16 MB, Assoc  16, LineSize  64
-----------*----  Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
-----------*----  Instruction Cache  11, Level 1,   64 KB, Assoc   4, LineSize  64
-----------*----  Unified Cache      22, Level 2,  512 KB, Assoc   8, LineSize  64
-----------*----  Unified Cache      23, Level 3,   16 MB, Assoc  16, LineSize  64
------------*---  Data Cache         12, Level 1,   32 KB, Assoc   8, LineSize  64
------------*---  Instruction Cache  12, Level 1,   64 KB, Assoc   4, LineSize  64
------------*---  Unified Cache      24, Level 2,  512 KB, Assoc   8, LineSize  64
------------*---  Unified Cache      25, Level 3,   16 MB, Assoc  16, LineSize  64
-------------*--  Data Cache         13, Level 1,   32 KB, Assoc   8, LineSize  64
-------------*--  Instruction Cache  13, Level 1,   64 KB, Assoc   4, LineSize  64
-------------*--  Unified Cache      26, Level 2,  512 KB, Assoc   8, LineSize  64
-------------*--  Unified Cache      27, Level 3,   16 MB, Assoc  16, LineSize  64
--------------*-  Data Cache         14, Level 1,   32 KB, Assoc   8, LineSize  64
--------------*-  Instruction Cache  14, Level 1,   64 KB, Assoc   4, LineSize  64
--------------*-  Unified Cache      28, Level 2,  512 KB, Assoc   8, LineSize  64
--------------*-  Unified Cache      29, Level 3,   16 MB, Assoc  16, LineSize  64
---------------*  Data Cache         15, Level 1,   32 KB, Assoc   8, LineSize  64
---------------*  Instruction Cache  15, Level 1,   64 KB, Assoc   4, LineSize  64
---------------*  Unified Cache      30, Level 2,  512 KB, Assoc   8, LineSize  64
---------------*  Unified Cache      31, Level 3,   16 MB, Assoc  16, LineSize  64

Logical Processor to Group Map:
****************  Group 0

@The Stilt

Do you have any idea why your Coreinfo looks different from everyone else's (running Windows 10)?

Theirs look like this:

Here is my Coreinfo output on windows 10 with an 1800x

Logical to Physical Processor Map:
**--------------  Physical Processor 0 (Hyperthreaded)
--**------------  Physical Processor 1 (Hyperthreaded)
----**----------  Physical Processor 2 (Hyperthreaded)
------**--------  Physical Processor 3 (Hyperthreaded)
--------**------  Physical Processor 4 (Hyperthreaded)
----------**----  Physical Processor 5 (Hyperthreaded)
------------**--  Physical Processor 6 (Hyperthreaded)
--------------**  Physical Processor 7 (Hyperthreaded)

Logical Processor to Socket Map:
****************  Socket 0

Logical Processor to NUMA Node Map:
****************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**--------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
**--------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
********--------  Unified Cache       1, Level 3,    8 MB, Assoc  16, LineSize  64
--**------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
--**------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
----**----------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
----**----------  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
------**--------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
------**--------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
--------**------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**------  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
--------**------  Unified Cache       5, Level 2,  512 KB, Assoc   8, LineSize  64
--------********  Unified Cache       6, Level 3,    8 MB, Assoc  16, LineSize  64
----------**----  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**----  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
----------**----  Unified Cache       7, Level 2,  512 KB, Assoc   8, LineSize  64
------------**--  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**--  Instruction Cache   6, Level 1,   64 KB, Assoc   4, LineSize  64
------------**--  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
--------------**  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**  Instruction Cache   7, Level 1,   64 KB, Assoc   4, LineSize  64
--------------**  Unified Cache       9, Level 2,  512 KB, Assoc   8, LineSize  64

 

[The Stilt]

@The Stilt

Do you have any idea why your Coreinfo looks different from everyone else's (running Windows 10)?

Theirs look like this:

Now that you asked, I most likely do.
I swapped the computers and didn't download Coreinfo from the link provided.
It appears that I have used 3.03 version of the program, instead of the newest one (3.31).

Why OS installs are fine as they are fully updated and not much more than a week old.
No 3rd party software installed, besides the drivers some internal tools, Steam & Origin.