@The Stilt What is your explanation of Ryzen not being fully utilized in games, even when there is no GPU bottleneck?
Is it something you've heard or just saying that for posterity?Raven isn't necessarily made on 14nm LPP
Games have to respond to your input,this means that no matter how multithreaded the game is,there is one thread that will always run at 100% of available one-core/single threaded and slowing down the multithreaded part of the game,if you want to see close to full utilization look at pure gpu benchmarks like the division or tomb raider with the fastest card possible and the smallest resolution possible.@The Stilt What is your explanation of Ryzen not being fully utilized in games, even when there is no GPU bottleneck?
Games have to respond to your input,this means that no matter how multithreaded the game is,there is one thread that will always run at 100% of available one-core/single threaded and slowing down the multithreaded part of the game,if you want to see close to full utilization look at pure gpu benchmarks like the division or tomb raider with the fastest card possible and the smallest resolution possible.
Because there are enough cores to juggle the threads around so none reaches 100% usage in task manager/msi because they are measuring over time.That wasn't the case though. No thread went up to 100% in most cases.
Why would the 1700 have less load (on average and in most case in most loaded thread), with no GPU bottleneck but less output (FPS)?
The combination of being:That wasn't the case though. No thread went up to 100% in most cases.
Why would the 1700 have less load (on average and in most case in most loaded thread), with no GPU bottleneck but less output (FPS)?
c) using 3x more memory at that particular point, and
The combination of being:
a) nowhere near full load on CPU,
b) noweher near full load on GPU,
c) using 3x more memory at that particular point, and
d) having circa 10-15 fps lower than the 7700k at the same time...
...is what I found strange.
What woud cause the memory usage to spike like that?
L1>L2>L3>DRAM, right...?
They both have similar L1 cache, R7 1700 has double L2 cache, and R7 1700 has access to more L3 cache, though through 2*CCXs.
The problem has to be with the L3, right?
I have a query or 2!
1. Re SMU data.. I notice HWinfo is reporting Core powers, package power. Is this accurate when in 'OC' mode, with custom Vcore? I ask because it seems to be reading lower than expected at higher vcores.
2. CPU-NB voltage. Does this have a new name? are still listing it as CPU-NB., and does athis plane acctually supply the DF?
So you're saying that cTDP limits total power draw over time, but only marginally limits peak turbo speeds. That's very interesting. Might we see mobile SKUs with specs along the lines of Ivy Bridge/Haswell 17W CPUs, with sub-2GHz Base clocks and ~+50% boost clocks (just 2-4x,the cores)? That would be very interesting. I'd gladly see 4c8t chips moving into the 15-25W mobile space, although with an iGPU thrown into the mix you'd probably need another 10+W of thermal headroom.
The power consumption reported by HWInfo for Zeppelin should be pretty accurate (I haven't validated it fully vs. DCR), however there are few conditions. The data displayed by HWInfo is based on SVI2 telemetry. The data originates from the VRM controller, however the issue is that it passes through the SMU where it technically could be altered / skewed to either direction. This is the exact reason why I never use the SVI2 telemetry for AMD or SVID data for Intel, for power consumption. Additionally, if you use these figures you must not change the Rll (load-line) resistance.
cTDP caps the total power consumption to a certain value.
The power consumption will never be exceeded, no matter the workload or number of utilized cores. It works exactly like a rev limiter in engines.
The performance impact of limiting the power consumption will naturally depend on the number of utilized cores and the workload. Obviously at e.g. 30W you will be able to run a single core close to its maximum XFR ceiling, while the "n" core stress frequency will be more limited.
On Zeppelin the capped figure is the "Package Power" (PP), unlike with all of the previous designs (excl. Carrizo / Bristol Ridge). This means that all of the different domains (e.g. PCIe Phys, peripherals, etc) are included to this power limit, not just the CPU cores & northbridge like with designs such as Orochi (PD), Kaveri (SR), etc. It is truly a total package power limit.
@The Stilt What is your explanation of Ryzen not being fully utilized in games, even when there is no GPU bottleneck?
Stilt, regarding base clock overclocking. I usually avoid it myself on Intel platforms because its not worth it as you cant really go over 110 BCLK in most cases, and SATA integrity begins to be a concern for me. But on AM4, does the base clock also alter SATA? Or just PCI-E? Because some people are sugesting to use base clock to overclock say a 1700 from 100 to 120, and make it work in PCI-E 2.0 mode. Won't the SATA CLK generator also be at 120, thus rapidly increasing the chances for data corruption? Base clock seems a good way to avoid the OC mode when overclocking nonetheless.
Second and last, does Zen play by the AMD book regarding tCTL? Are we still with the "these are not real temps, it's just an internal scale made by AMD and you can't just go above X arbritrary number (think it was 72 on Vishera/FX forE.G)"?. I take tCASE became irrelevant this round as the socket infraestructure isn't as compromised as it was with FX chips on AM3+.
I highly doubt 14nm LPP was what AMD wanted and it was definitely not suitable for HEDT. It looks like it was just what was available for HVM, and is heavily suitable for Mobile.Is it something you've heard or just saying that for posterity?
@TheStilt, what kind of software fixes would be needed for the OS? scheduler/kernel patches? or rather the USB etc kind of driver support for the integrated chipset?
Also at BIOS level which kind of patches are applied, Timings and Circuitry logic or also micro code?
850 points in Cinebench 15 at 30W is quite telling. Or not telling, but absolutely massive. Zeppelin can reach absolutely monstrous and unseen levels of efficiency, as long as it operates within its ideal frequency range.
This is the dealmaker as a server chip right?
(also, why is this review in at forums? should have its own space imo)
I'm not familiar with the potential issues at OS side.
I'd say SMU, PMU (DRAM) firmwares and the microcode are the ones which will have most of the potential improvements & refinements.
I think the memory refers to VRAM and not system memory.