Ryzen, Skylake, and everything that's coming next. (MEGA discussion thread)

[Ajay]

It will be interesting to see when AMD transfers this to GPU with Navi. Imaginge how performance and pricewise the fusing of 2 300mm dies will compete with an 600mm die.
Interesting times ahead of us.

Seems like that would be a much more difficult engineering problem.

 

[Ajay]

They used an MCM with Magny Cours and the Bulldozer stuff. This is not a new strategy and it is certainly not revolutionary as some seem to think, IMHO.

True, but it looks like AMD has learned allot and will be leveraging the capability better this time. We'll have to see how EPYC performs to know for sure.

 

[R0H1T]

Seems like that would be a much more difficult engineering problem.

Something something like the insides of Scorpio, except on a much larger scale plus complexity?

 

[krumme]

It isn't and that is why you are wrong. It's the interconnect on everything, It's the interconnect for CCX's, it's the interconnect on the GPU dies. It's the interconnect between CPU and GPU on the same die in APU's, it's an interconnect that allows the CPU to be an hbc connector to on-board memory. It's least important connection aspect is CPU dies to CPU dies.

As The Stilt have show the bandwith is plenty between ccx. That leaves latency.
But is Intel solution better then?

From a business perspective certainly not for amd with their portfolio and embedded focus. One thing is that IF connect all their technology it also speeds up TTM and that gives huge flexibility in case they want to change direction. The first means reduced cost the second is reduced risk and thats also in practice equal to money in the bank.

From a top management perspective its a dream tool.

 

[Vaporizer]

Seems like that would be a much more difficult engineering problem.

This might be the reason for Navi being scalable in 2018/2019 and not already this year like ryzen.

 

[imported_ats]

Zen/Zeppelin are the major accomplishments along with IF. Before even on MCM the dies communicated through FSB. Now AMD has a platform that will allow almost single die loke communication between Dies not only on socket but between them. MCM is old, AMD leveraging MCM to us IF to ramp up the cores at a relatively low cost is revolutionary. AMD can provide almost linear compute growth all the way up 64 cores and 128 threads through $450 in silicon. The big question in EPYC and across sockets what the cache performance (not just latency, but how the cache is handled).

Um, previous products were connected with an interconnection network as well. There is nothing really novel here. IF is just basically HT++. And no, it won't allow single die like communications between dies. If it was a single die the communication bandwidth would be significantly higher and the latency would be significantly lower. There is nothing revolutionary about it, it is LITERALLY the same strategy they have employed for the last decade+. Nor can they provide linear compute growth in any different degree than what they've provided for a decade plus.

Zen is not revolutionary in any regard. If AMD had properly evolved Athlon/Opteron correctly without their P4 like detour into bad design, they would be pretty much exactly where they are.

 

[Topweasel]

Um, previous products were connected with an interconnection network as well. There is nothing really novel here. IF is just basically HT++. And no, it won't allow single die like communications between dies. If it was a single die the communication bandwidth would be significantly higher and the latency would be significantly lower. There is nothing revolutionary about it, it is LITERALLY the same strategy they have employed for the last decade+. Nor can they provide linear compute growth in any different degree than what they've provided for a decade plus.

Zen is not revolutionary in any regard. If AMD had properly evolved Athlon/Opteron correctly without their P4 like detour into bad design, they would be pretty much exactly where they are.

I can't speak for BD based MCM. But I know the phenom MCM used the FSB.

In March 2010 AMD released the Magny-Cours Opteron 6100 series CPUs for Socket G34. These are 8- and 12-core multi-chip module CPUs consisting of two four or six-core dies with a HyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for the Istanbul CPUs to 3.20 GHz (6.40 GT/s)

Speed isn't the only point. AMD is using IF as an internal communication tools along with being an external communication tool. Since its the same on same between ccx, as mcm, as between sockets, the potential is to allow for the whole system too act as one large cpu with shared resources instead of two cpu's on one mcm and 4 across 2 sockets. Or in this case for and 8 respectively.

 

[imported_ats]

I can't speak for BD based MCM. But I know the phenom MCM used the FSB.

No, no they didn't. All Phenom products were HT based. AMD hasn't used a shared FSB since K6. K7 used the EV6 interface which was a point to point interface with bi-direction data interface and 2 unidirectional control interfaces. K8 moved to HT which is a packetized point-to-point interconnection network.

Speed isn't the only point. AMD is using IF as an internal communication tools along with being an external communication tool. Since its the same on same between ccx, as mcm, as between sockets, the potential is to allow for the whole system too act as one large cpu with shared resources instead of two cpu's on one mcm and 4 across 2 sockets. Or in this case for and 8 respectively.

That's basically more BS. They *might* use the same protocol on-chip between CCX, but that means jack all when it comes to this panacea idea you have. The physical characteristics are fundamentally different on chip, on mcm, and between mcms. You are talking about some pie in the sky fantasy land that simply does not and never will exist.

 

[krumme]

Is production platforms revolutionary? Or object oriented programming?
The results surely is while the concepts might be ordinary and simple and looks like how we "have always done it"

What make IF interesting is to what degree there is set rules. The detailed level of standards. From witch they can form eg the nessesary protocols.

Think of IF as rules of engagement everyone in the organization will have to follow. It means predefined bigger building blocks ready for use but also loads of minor rules.

It speeds up development like nothing else.
Normally engineers or bean counters have their world view and when starting a project everyone have the ambition it should be the best possible. Truckloads of meetings begin to make the perfect wheel. Its a dicipline engineers love but it takes time.

Ryzen core and IF is not the invention of a new wheel or to "make the ocean boil" and thats excactly why its successfull.

 

[Topweasel]

No, no they didn't. All Phenom products were HT based. AMD hasn't used a shared FSB since K6. K7 used the EV6 interface which was a point to point interface with bi-direction data interface and 2 unidirectional control interfaces. K8 moved to HT which is a packetized point-to-point interconnection network.

EV6 was a normal FSB it had features like DDR comunication and higher clock speeds than Intel's old FSB at the time. But it was still an old fashion FSB. To me HT was a FSB as well even though it was point to point all that really changed is that AMD put on Mem controller on die and ratcheted up the connection to the Chipset with a super high bandwidth connector. All it was really missing is the memory connecting into it. And it's implementation never really rose from that.

That's basically more BS. They *might* use the same protocol on-chip between CCX, but that means jack all when it comes to this panacea idea you have. The physical characteristics are fundamentally different on chip, on mcm, and between mcms. You are talking about some pie in the sky fantasy land that simply does not and never will exist.

I'll leave this alone. You obviously haven't been keeping a close enough watch on IF. But even if lets say you are right. You are saying that there will never ever be an interconnect that would allow cache sharing between CPU's on different sockets? I mean never? Like even a 100 years out? I just can't believe that you could be that limited in foresight and ingenuity that you think that even if it's not capable now, that it isn't one of the eggs that Intel and AMD want to crack and could eventually pull it off.

 

[imported_ats]

EV6 was a normal FSB it had features like DDR comunication and higher clock speeds than Intel's old FSB at the time. But it was still an old fashion FSB. To me HT was a FSB as well even though it was point to point all that really changed is that AMD put on Mem controller on die and ratcheted up the connection to the Chipset with a super high bandwidth connector. All it was really missing is the memory connecting into it. And it's implementation never really rose from that.

No, EV6 bus wasn't a normal FSB. It was a point to point connection. DDR communication is standard on just about every interconnect from processor interconnection networks like QPI/HT to networking physical layers like ethernet. EV6 supports 1 processor die per bus connected to a chipset. It doesn't allow 2 cpu dies to share it. And if you consider HT to be FSB, then IF is FSB. HT was used to connect both multiple sockets and multiple dies within a socket. In fact, the network map between 8 Zen dies and 8 opteron dies looks pretty much the same.

I'll leave this alone. You obviously haven't been keeping a close enough watch on IF. But even if lets say you are right. You are saying that there will never ever be an interconnect that would allow cache sharing between CPU's on different sockets? I mean never? Like even a 100 years out? I just can't believe that you could be that limited in foresight and ingenuity that you think that even if it's not capable now, that it isn't one of the eggs that Intel and AMD want to crack and could eventually pull it off.

No that isn't what I'm saying NOR is it what you said earlier. We've had interfaces that allow cache sharing between cpu's on different sockets longer than you've likely been alive. This was in fact true for K7, k8, and bd, all allowed cache sharing between CPU's. IBM mainframes have literally allowed it for decades. That is literally the definition of a coherent multi-processor which as I said, have likely existed longer than you've been alive. THAT is nothing to do with what you are claiming makes IF special. Unless you want to say that IF doesn't do anything that wasn't already done back in the 60s.

 

[imported_ats]

Is production platforms revolutionary? Or object oriented programming?
The results surely is while the concepts might be ordinary and simple and looks like how we "have always done it"

What make IF interesting is to what degree there is set rules. The detailed level of standards. From witch they can form eg the nessesary protocols.

Think of IF as rules of engagement everyone in the organization will have to follow. It means predefined bigger building blocks ready for use but also loads of minor rules.

It speeds up development like nothing else.
Normally engineers or bean counters have their world view and when starting a project everyone have the ambition it should be the best possible. Truckloads of meetings begin to make the perfect wheel. Its a dicipline engineers love but it takes time.

Ryzen core and IF is not the invention of a new wheel or to "make the ocean boil" and thats excactly why its successfull.

Um, you mean like HT, or EV6 bus or P6 bus or QPI or EV7 interconnection network or SGI's NUMAlink or ARM's AMBA or IB or ethernet or USB or by god a simple ancient serial port (take your pick RS-232/422/485)? Cause literally everything you've said applies to them. What you describe is called in engineering circles as a "specification". Those are everywhere.

 

[Whitestar127]

So, I was sure Ryzen 1600X was going to be my next CPU. But rumor has it Coffee Lake will have about 30 % better performance than the 7700K and 6 cores? Hmmm, things got complicated again.

 

[tamz_msc]

So, I was sure Ryzen 1600X was going to be my next CPU. But rumor has it Coffee Lake will have about 30 % better performance than the 7700K and 6 cores? Hmmm, things got complicated again.

That 30% figure is when comparing a 2C/4T mobile chip to a 4C/8T mobile chip at 15W TDP.

 

[Topweasel]

So, I was sure Ryzen 1600X was going to be my next CPU. But rumor has it Coffee Lake will have about 30 % better performance than the 7700K and 6 cores? Hmmm, things got complicated again.

Expect Coffee lake to be 6c at best at Skylake clocks. So roughly 4Ghz. That will be a much faster 6c CPU than the 1600x. I wouldn't expect much in terms of IPC increase. Almost all of the "increase" KL had over SL was in clockspeed.

 

[Topweasel]

Stuff

I honestly have zero energy for this conversation anymore. You don't think IF is important even though AMD themselves says that IF is more important to their future then Zen or any other singular product. If you haven't read anything that piques your interest in it and you think it's the same old wheel as before then fine. But that's it I am done and you are going on my ignore list. This seems to bring out the worst in people. 17 years almost and I hadn't blocked a single user. In the last months I have had to block 3.

 

[imported_ats]

I honestly have zero energy for this conversation anymore. You don't think IF is important even though AMD themselves says that IF is more important to their future then Zen or any other singular product. If you haven't read anything that piques your interest in it and you think it's the same old wheel as before then fine. But that's it I am done and you are going on my ignore list. This seems to bring out the worst in people. 17 years almost and I hadn't blocked a single user. In the last months I have had to block 3.

No, I haven't seen anything about IF that is in any way really different than any other interconnection network and I've worked with and designed multiple cpu interconnection networks and studied them for literally decades. And beyond that, there are no actual details available about IF that are the least bit interesting, just marketing slides. We still don't know internal chip details, we still don't know the coherency protocol nor do we know actual speeds and feeds and signalling. There just isn't enough detail to even get to the interesting parts of an interconnection network: what are the packet formats, what are the outstanding request limitations, what are the routing abilities, what are the simple and complex protocol flows, etc.

 

[Whitestar127]

That will be a much faster 6c CPU than the 1600x.

Because of the IPC?

 

[maddie]

No, I haven't seen anything about IF that is in any way really different than any other interconnection network and I've worked with and designed multiple cpu interconnection networks and studied them for literally decades. And beyond that, there are no actual details available about IF that are the least bit interesting, just marketing slides. We still don't know internal chip details, we still don't know the coherency protocol nor do we know actual speeds and feeds and signalling. There just isn't enough detail to even get to the interesting parts of an interconnection network: what are the packet formats, what are the outstanding request limitations, what are the routing abilities, what are the simple and complex protocol flows, etc.

I can see the AMD teams almost praying the competitors think this to be the case. Keep believing there's been nothing really changed and continue business as usual. The next 2 years are going to be very important to reestablish strong market positions in both CPUs &GPUs. There are going to be some great affordable performance advances coming.

 

[Topweasel]

Because of the IPC?

Because of IPC and clock speeds. The 1600x can in some games use it's extra resources to make a run at the 7600k and 7700k. But realistically they are down ~15% on IPC and 15% on clock speed. A 4ghz base clocked CL 8700k would now have the same amount of resources, a 5-10% clock speed advantage and at minimum a 15% IPC advantage.

 

[imported_ats]

I can see the AMD teams almost praying the competitors think this to be the case. Keep believing there's been nothing really changed and continue business as usual. The next 2 years are going to be very important to reestablish strong market positions in both CPUs &GPUs. There are going to be some great affordable performance advances coming.

IF doesn't fundamentally change anything. AMD will live or die and their products will live or die by attributes that have nothing to do with IF. If AMD reestablish strong market positions in CPUs, it will be because they offer value and performance which is largely independent of IF. Graphics is even more so independent of IF, first they need to ship actually competitive solutions which is something they largely haven't for quite some time, unfortunately. Stop putting so much faith in marketing slides and magic buzzword that you don't understand.

 

[AtenRa]

6C 12T Coffelake will be much faster than R5 1600X both in ST and MT, but it will also be more expensive.

 

[maddie]

IF doesn't fundamentally change anything. AMD will live or die and their products will live or die by attributes that have nothing to do with IF. If AMD reestablish strong market positions in CPUs, it will be because they offer value and performance which is largely independent of IF. Graphics is even more so independent of IF, first they need to ship actually competitive solutions which is something they largely haven't for quite some time, unfortunately. Stop putting so much faith in marketing slides and magic buzzword that you don't understand.

I have the completely opposite opinion. AMD will live or die and their products will live or die by attributes that have everything to do with IF.

Amd will live or die on the ability of IF to tie smaller sub-units into a seamless whole.

Sure, one can argue that interconnects have always existed and that you have personal experience with them. So what? Are you subtly claiming that because you don't know the details of something it cannot exist? Are you claiming that there can be no more advances in the technologies?

You claim that no one outside AMD know any real deep details about IF yet you outright claim there is nothing new here. I for one, am very confused now.

AMD has obviously embarked on a design once - use many strategy. To do this efficiently, they needed a unifying glue for the component parts. This is IF and why they state that it is the most important part of their new tech.

Everything they design and release for the next few years at least will need IF to function properly.

Do you really think AMD with its financial troubles could design separate 32 core, 16 core, 8 core and 4 core CPUs. IF allows them to release these different classes of products in what is an extremely short period of time with a very low development cost relative to the alternative. I'm sure you've heard of force multipliers, I'm just mystified at your hard rejection of the tech.

 

[krumme]

IF doesn't fundamentally change anything. AMD will live or die and their products will live or die by attributes that have nothing to do with IF. If AMD reestablish strong market positions in CPUs, it will be because they offer value and performance which is largely independent of IF. Graphics is even more so independent of IF, first they need to ship actually competitive solutions which is something they largely haven't for quite some time, unfortunately. Stop putting so much faith in marketing slides and magic buzzword that you don't understand.

We know the perf already in ryzen between ccx and its working plently fine. We dont know inter die or socket yet but The Stilt says its up there. So its actually performing. Its evident and not only ppt slide bs.

You dont seem to grasp or understand its not a simple bus standard but a framework for how they can also design gpu and cpu. Perhaps its a bit to abstract and probably goes beyond the level you have worked on it. Fair enough. Thats how progress is. And obviously you need good cpu and gpu ip also. No reason to state the obvious. Ev6 whatever is probably similar a long stretch but its excactly the extend that makes the difference.
Amd claims its major and they already have the first results to back that up. Its an excellent start but we also need eg the next tr and epyc perf to be up there.

 

[majord]

on the other end of the spectrum. Has there been any indication that Banded Kestrel will ever come to AM4? or are we only going to see harvested Raven Ridge to fill the low end?

Seems it would be potentially extremely competitive with intel's i3 and Celeron line.