RWT summarizes multiple foundries presentations on the 22nm node from ISSCC

[Martimus]

http://www.realworldtech.com/page.cfm?ArticleID=RWT031411013528&p=1

Most of the discussion went well over my head. Or at least didn't hold my interest enough for me to read through completely. However I did find a few interesting points in the article. One, Both Intel and TSMC are planning on switching to 450mm wafers, while GF and IBM are not. (TSMC has already commited to 450mm wafers at the 20nm node). Second, Intel went over how double patterning can really save money due to less capital expenditures, and is useful for any process so it is good to gain experience using it.

Mark Bohr of Intel made a contrarian point about the costs of double patterning, which most of the panelists considered to be unattractive. It seems expensive to reduce throughput by using two exposures on critical layers, since it reduces throughput. However, double patterning significantly reduces capital expenditures, since the expensive lithography equipment can be re-used across future generations. In contrast, using immersion lithography to achieve the same benefits requires new equipment and introduces yield risks. Moreover, judicious use of RDRs can mitigate the number of layers that need double patterning and thus the throughput impact. Additionally, double patterning is manufacturing techniques that works with almost any type of lithography and is a valuable skill to master going forward.

The last and least surprising difference was on 450mm wafers. Intel and TSMC clearly believe that increasing wafer size will significantly improve the cost structure for manufacturing. TSMC has even publicly committed to a 450mm fab for the 20nm node. Global Foundries and IBM were much less enthusiastic about the prospect and were concerned with the increased cost of process technology development and fabs. This is entirely expected since Intel and TSMC have substantially higher volumes and are willing to increase their capital expenditures to reduce variable costs.

 

[Idontcare]

I'm surprised that EUV did not even get a passing mention by the panelist. I never in a million years would have thought we'd see 450mm fabs before EUV finally went to production. I remember when 157nm litho was killed off as the leading candidate for NGL and everyone was saying it was ok because EUV was right around the corner.

EUV and Itanium sales forecasts must have been done by the same guy...I hear he's recently been let go from team DNF.

And there is a rather big difference in the cost-structure for an Intel to go double-patterning versus a foundry. All those extra masks add up in cost, in a big way, not such a big deal if you are amortizing the mask-adder cost across tens of millions of chips but if you are a foundry customer your wafer runs might only be 500-1000 wfrs total and the cost of a single mask adder can make the difference between profitable and not profitable for the customer.

I once spent 4 yrs working on a project whose sole claim to existence was that it was a single-mask adder component versus the competition's requiring 2-masks. The cost difference when it netted out at the product level in a foundry environment (where the mask adder count is multiplied by the number of customer designs) is a huge driver for simplified lithography even if it means more expensive litho up-front.

 

[Martimus]

Global Foundries did commit to buy a production EUV tool from ASML, but I have yet to hear any word on how they planned to get around the current lack of throughput the tool can produce.

 

[Hacp]

Very good summary explaining the challenges of chip design. As a layman who knows very little about electrical engineering, it made perfect sense.