Discussion RISC V Latest Developments Discussion [No Politics]

[DisEnchantment]

Some background on my experience with RISC V...
Five years ago, we were developing a CI/CD pipeline for arm64 SoC in some cloud and we add tests to execute the binaries in there as well.
We actually used some real HW instances using an ARM server chip of that era, unfortunately the vendor quickly dumped us, exited the market and leaving us with some amount of frustration.
We shifted work to Qemu which turns out to be as good as the actual chips themselves, but the emulation is buggy and slow and in the end we end up with qemu-user-static docker images which work quite well for us. We were running arm64 ubuntu cloud images of the time before moving on to docker multi arch qemu images.

Lately, we were approached by many vendors now with upcoming RISC-V chips and out of curiosity I revisited the topic above.
To my pleasant surprise, running RISC-V Qemu is smooth as butter. Emulation is fast, and images from Debian, Ubuntu, Fedora are available out of the box.
I was running ubuntu cloud images problem free. Granted it was headless but I guess with the likes of Imagination Tech offering up their IP for integration, it is only a matter of time.

What is even more interesting is that Yocto/Open Embedded already have a meta layer for RISC-V and apparently T Head already got the kernel packages and manifest for Android 10 working with RISC-V.
Very very impressive for a CPU in such a short span of time. What's more, I see active LLVM, GCC and Kernel development happening.

From latest conferences I saw this slide, I can't help but think that it looks like they are eating somebody's lunch starting from MCUs and moving to Application Processors.


And based on many developments around the world, this trend seems to be accelerating greatly.
Many high profile national and multi national (e.g. EU's EPI ) projects with RISC V are popping up left and right.
Intel is now a premium member of the consortium, with the likes of Google, Alibaba, Huawei etc..
NVDA and soon AMD seems to be doing RISC-V in their GPUs. Xilinx, Infineon, Siemens, Microchip, ST, AD, Renesas etc., already having products in the pipe or already launched.
It will be a matter of time before all these companies start replacing their proprietary Arch with something from RISC V. Tools support, compiler, debugger, OS etc., are taken care by the community.
Interesting as well is that there are lots of performant implementation of RISC V in github as well, XuanTie C910 from T Head/Alibaba, SWerV from WD, and many more.
Embedded Industry already replaced a ton of traditional MCUs with RISC V ones. AI tailored CPUs from Tenstorrent's Jim Keller also seems to be in the spotlight.

Most importantly a bunch of specs got ratified end of last year, mainly accelerated by developments around the world. Interesting times.

 

[soresu]

Well, Jim Keller's compay (Tenstorrent) finally released their 8-wide OoO RISC-V design, Ascalon IP (for others to implement)

IIRC Ascalon is actually multiple µArch designs of different complexity/power/area, with the 8 wide implementation being the highest end offering.

Will be interesting to see it up against SiFive's Napa µArch which is supposed to be their future hi end offering.

 

[Jan Olšan]

IIRC Ascalon is

Is "is" a good term for a vaporware product that doesn't seem to exist in silicon? Not that I don't root for it but I kind of remember for how was K11 the talk of the internet for it to never happen.

 

[soresu]

Is "is" a good term for a vaporware product that doesn't seem to exist in silicon?

From the description it's synthesizable core IP, just like ARM CPUs and GPUs, as they have never espoused plans to the effect of separate CPUs it would be unlikely for them to have it in silicon outside of test samples.

I doubt Jim Keller would have pinned his name to vaporware, whether the perf is any good is another question.

 

[DZero]

glofo acquired one more RISC ip

https://twitter.com/x/status/2011665310127165842

https://twitter.com/x/status/1998061552503533936

https://x.com/IanCutress/status/2011442535722590241?s=20

Isn't MIPS being deader than dead?

 

[LightningZ71]

It's still very relevant in the embedded, automotive and edge space. However, the ISA is being slowly left behind for RISC-V.

 

[LightningDust]

Isn't MIPS being deader than dead?

Legacy MIPS cores have been souped-up and ported to RV to form the current MIPS product lineup. (Note the similarity of MIPS I8500, which is RISC-V, to the MIPS-based I6500, and likewise P8700 to P6600 - though P8700 at least adds SMT.)

Intel (Mobileye) is buying. I have no idea who else is.

Also, RIP ARC. Some nice IP, and ARC64 was practically brand new.

 

[Nothingness]

Also, RIP ARC. Some nice IP, and ARC64 was practically brand new.

Perhaps Global Foundries will make something with these chips, I think there still are customers. But it's likely only ARC-V will survive.

This reminds me I was almost recruited to work on the gcc back-end for ARC by Jez San back in 96 or 97. I finally declined because moving to UK was not an option.

 

[LightningDust]

Perhaps Global Foundries will make something with these chips, I think there still are customers. But it's likely only ARC-V will survive.

There are - far more for ARC (including a couple for ARC64/ARCv3) than for ARC-V, at least so far.

But while I personally like the ARC value proposition, I'm also pretty aware that it was never much more than an also-ran, especially compared to Xtensa, which has basically the same target market and several times the volume.