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CISC is the generally accepted answer for both the Athlon and the Pentium, although it's more accurate to say that they both have a RISC like core and a layer that translates the CISC instructions into micro-ops.
"In the end, I'm not calling the Athlon or P6 "RISC," but I'm also not calling them "CISC" either. The same goes for the G3 and G4, in reverse. Indeed, in light of what we now know about the the historical development of RISC and CISC, and the problems that each approach tried to solve, it should now be apparent that both terms are equally nonsensical when applied to the G3, G4, MIPS, P6, or K7. In today's technological climate, the problems are different, so the solutions are different. Current architectures are a hodge-podge of features that embody a variety of trends and design approaches, some RISC, some CISC, and some neither. In the post-RISC era, it no longer makes sense to divide the world into RISC and CISC camps. Whatever "RISC vs. CISC" debate that once went on has long been over, and what must now follow is a more nuanced and far more interesting discussion that takes each platform--hardware and software, ISA and implementation--on its own merits."
By the way, the G4 is fast becoming passe in the desktop world. The future of PowerPC is the IBM PPC 970.
But the terms have little meaning any more outside of academia. The Athlon and Pentium 4 both take a CISC instruction set and decode them into RISC micro-ops and the G4's RISC-like instruction set has been looking increasingly less RISC-like as the design matures. I'd say all three should really be catagorized as a mix of the two types.
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