News Report claims that Intel will build Core i3s at TSMC

[NTMBK]

Reporting from Tom's Hardware here, and the actual report from Trendforce here.

Intel has outsourced the production of about 15-20% of its non-CPU chips, with most of the wafer starts for these products assigned to TSMC and UMC, according to TrendForce’s latest investigations. While the company is planning to kick off mass production of Core i3 CPUs at TSMC’s 5nm node in 2H21, Intel’s mid-range and high-end CPUs are projected to enter mass production using TSMC’s 3nm node in 2H22.

...

TrendForce believes that increased outsourcing of its product lines will allow Intel to not only continue its existence as a major IDM, but also maintain in-house production lines for chips with high margins, while more effectively spending CAPEX on advanced R&D. In addition, TSMC offers a diverse range of solutions that Intel can use during product development (e.g., chiplets, CoWoS, InFO, and SoIC). All in all, Intel will be more flexible in its planning and have access to various value-added opportunities by employing TSMC’s production lines. At the same time, Intel now has a chance to be on the same level as AMD with respect to manufacturing CPUs with advanced process technologies.

I have no idea how credible Trendforce are, or what their track record is, but they seem pretty confident. Sounds like Intel might be pivoting their internal fabs to be "IBM-like"- lower volume, higher margin products, tuned to absolute max performance, and don't need to yield high enough to manufacture cheap PC chips.

 

[Doug S]

Of all the rumors so far, I consider i3's one of the less likely target for outsourcing.

That seems the most likely to me, because they can use an N+1 process. In order to do their leading edge stuff Intel has to get leading edge wafer allocations from TSMC, where they will be waiting in line behind established customers Apple, AMD and perhaps Qualcomm (who seems to switch between TSMC and Samsung)

Not to mention the huge PR black eye they'd have from not making their high end stuff in their own fabs.

 

[Heartbreaker]

That seems the most likely to me, because they can use an N+1 process. In order to do their leading edge stuff Intel has to get leading edge wafer allocations from TSMC, where they will be waiting in line behind established customers Apple, AMD and perhaps Qualcomm (who seems to switch between TSMC and Samsung)

Not to mention the huge PR black eye they'd have from not making their high end stuff in their own fabs.

That really doesn't hold water.

If they need TSMC, it will be to regain leading edge competitive performance, that their trailing process can't deliver.

i3 doesn't need leading edge performance. It's a budget part, perfect for Intel Trailing processes, and it will be cheaper to manufacture on their in house.

Paying more money for leading edge external process for the budget parts, is pretty much the exact opposite of what they should do.

 

[jpiniero]

i3 doesn't need leading edge performance. It's a budget part, perfect for Intel Trailing processes, and it will be cheaper to manufacture on their in house.

But if it has to be Alder Lake, and they don't have room on 10 nm because they are compensating for the mediocre at best yield, they don't have any in house options. This is where being chiplets (and the IGP on 14 nm) would have helped tremendously.

 

[blckgrffn]

I am not bullish on this, but if they are going to send a part over for 6nm or similar then it would be similar to the first 10nm parts - i3, min GPU spec to confirm it “works” and use those parts for a particular OEM partner only. Chromebooks specials outside the typical realm of what we care about.

The process might inform later decisions. There is no real test like bringing a product all the way to production.

 

[french toast]

Wait a minute, hasn't Apple bought up all the 5nm production for 2021?
I would also bet good money that they buy the bulk of 3nm in 2022 as well.

In an ideal world if they do outsource they would want their mainstream and budget processors on Tsmc 7nm..
Great yield and performance, loads of capacity, probably cheap as well.
Then they could use their own process for their halo parts.

The only real scenario I could see them going against this is if the whole thing got messed up and swapped, Alderlake locked in for 10nm+++ and not getting great yield/wafers for planned mainstream, - - forcing them to outsource products on expensive processes they would rather not.
Why would Tsmc give them their best processes anyway?

 

[jpiniero]

Wait a minute, hasn't Apple bought up all the 5nm production for 2021?

Maybe TSMC is adding more capacity and that's what they offered Intel.

 

[Hulk]

Do we really know how far Intel's 10SF is actually behind TMSC's 7nm? Tiger Lake is hitting 4.8GHz single core with all core turbo of 4.3GHz at 52 Watts (package) according to the Anandtech review and this is for the less efficient Willow Cove core.

Doing some quick napkin math, for 12 cores that would be ~156 Watts. 5900X according to Anandtech is at 4.15 GHz clock drawing129 Watts. Back the Tiger Lake cores down from 4.3 to 4.15 GHz and it seems as though the power draw would be pretty close.

I realize I'm comparing AMD's desktop part against Intel's mobile but I'm just saying Intel's 10SF might not actually be that far behind TMSC's 7nm.

Intel’s Tiger Lake 11th Gen Core i7-1185G7 Review and Deep Dive: Baskin’ for the Exotic

www.anandtech.com

AMD Zen 3 Ryzen Deep Dive Review: 5950X, 5900X, 5800X and 5600X Tested

www.anandtech.com

 

[french toast]

Maybe TSMC is adding more capacity and that's what they offered Intel.

Maybe, why AMD didn't snatch that up is anyone's guess, they need all the capacity they can get, they would easily sell any premium 5nm part they could make.

All I know is warhol better offer some decent clock boosts.

 

[french toast]

Do we really know how far Intel's 10SF is actually behind TMSC's 7nm? Tiger Lake is hitting 4.8GHz single core with all core turbo of 4.3GHz at 52 Watts (package) according to the Anandtech review and this is for the less efficient Willow Cove core.

Doing some quick napkin math, for 12 cores that would be ~156 Watts. 5900X according to Anandtech is at 4.15 GHz clock drawing129 Watts. Back the Tiger Lake cores down from 4.3 to 4.15 GHz and it seems as though the power draw would be pretty close.

I realize I'm comparing AMD's desktop part against Intel's mobile but I'm just saying Intel's 10SF might not actually be that far behind TMSC's 7nm.

Intel’s Tiger Lake 11th Gen Core i7-1185G7 Review and Deep Dive: Baskin’ for the Exotic

www.anandtech.com

AMD Zen 3 Ryzen Deep Dive Review: 5950X, 5900X, 5800X and 5600X Tested

www.anandtech.com

My guess is Intel 10SF is superior to TSMC N7 in pure clock potential, less so in all other metrics.

 

[mikk]

I have to agree, TSMC seems to have a better efficiency curve and the pure clock speed potential is a bit behind, based on Zen3 and Tigerlake clock speed abilities. This being said, Alder Lake will be based on an enhanced SuperFin node. So I think they will be fine against TSMC 7nm chips. What happens when AMD is ready with 5nm chips is another question.

 

[Exist50]

I have to agree, TSMC seems to have a better efficiency curve and the pure clock speed potential is a bit behind, based on Zen3 and Tigerlake clock speed abilities. This being said, Alder Lake will be based on an enhanced SuperFin node. So I think they will be fine against TSMC 7nm chips. What happens when AMD is ready with 5nm chips is another question.

Clock speed depends heavily on design, not just fab process.

 

[moinmoin]

The big issue Intel faces is not the technical competitiveness of its nodes (which is fine despite the effectively half a decade node advantage lost so far) but the actual yield it manages on them. The fact that it only launched small dies on 10nm so far (with Ice Lake SP still to be seen) tell us that the current yield makes bigger dies not worth the cost yet.

Intel's conundrum for a long time was that 14nm is way too profitable to even bother with 10nm and 7nm. Now since outsourcing to TSMC is seriously considered the cost for improving the yield appears to be still higher than the costs associated with porting designs to TSMC's node and then pay them per die which should add up to significantly more than internally produced dies if Intel's node development weren't strewn with setbacks. And that says it all really.

 

[Hulk]

Clock speed depends heavily on design, not just fab process.

Intel seem to generally out-clock AMD so I think they design for high frequencies effectively.

 

[Doug S]

Maybe TSMC is adding more capacity and that's what they offered Intel.

A fab can't easily add leading edge capacity quickly. They would need customer orders or at least projections a year+ in advance to adjust future capacity.

However, with 5nm the limitation would be more to do with the number of EUV scanners they have. ASML is making them as fast as they can, but they have a backlog and not only TSMC but also Samsung and Intel are buying them. If they are limited in the number of N5/N5P wafers they can offer in 2021 you bet Apple gets allocated everything they want before anyone else gets a look in thanks to them paying in advance. AMD is probably right there behind them saying we want to buy everything that's left.

Which is probably why Qualcomm went to Samsung this time around.

I don't see much chance of Intel getting any TSMC 5nm wafers until H2 2022 when they begin 3nm production and Apple's 5nm demand begins easing off. But AMD may have taken steps to soak all that up themselves.

It just doesn't seem reasonable that Intel is going to get any more than a token amount of TSMC's 5nm wafers in the next two years, unless they make a deal like an EUV scanner swap where they give TSMC some of their orders arriving sooner in exchange for TSMC orders arriving later. It isn't like Intel has any use of them right now...

 

[moinmoin]

Intel seem to generally out-clock AMD so I think they design for high frequencies effectively.

That's sure is the one skill Intel honed with its series of Skylake on 14nm remakes...

 

[Hulk]

That's sure is the one skill Intel honed with its series of Skylake on 14nm remakes...

You do what you have to survive. If you have to go into the heating business as a side job you do it.

 

[mikk]

That's sure is the one skill Intel honed with its series of Skylake on 14nm remakes...

....which is process related. The architecture is from 2015 no matter what remake, the clock speeds back in 2015 was nothing to write home about. All the clock speed improvements over the years came with the improvements from Intels 14nm. And also Icelake is a good example, it clocked poorly on the first 10nm version.

 

[Exist50]

....which is process related. The architecture is from 2015 no matter what remake, the clock speeds back in 2015 was nothing to write home about. All the clock speed improvements over the years came with the improvements from Intels 14nm. And also Icelake is a good example, it clocked poorly on the first 10nm version.

Subsequent steppings can also provide clock boosts.

 

[DrMrLordX]

The big issue Intel faces is not the technical competitiveness of its nodes (which is fine despite the effectively half a decade node advantage lost so far) but the actual yield it manages on them. The fact that it only launched small dies on 10nm so far (with Ice Lake SP still to be seen) tell us that the current yield makes bigger dies not worth the cost yet.

Also keep in mind that Intel announced yet more 4c Tiger Lake parts without announcing an actual 8c SKU (yet):

They've pushed 8c Tiger Lake so far out that it is beginning to overlap with the potential launch dates for Alder Lake-S.

 

[moinmoin]

And also Icelake is a good example, it clocked poorly on the first 10nm version.

Why mention Ice Lake if you could have mentioned Cannon Lake?

And I don't think high frequencies is that much process related necessarily. AMD significantly raised frequencies between Zen 2 (which itself was already an improvement over GloFo's frequencies) and Zen 3, both on essentially the same N7 process. Yes, it was also improved, but the difference between Zen 2 XT and Zen 3 showed the frequency improvements were down to the silicon design, with XT not being close to Zen 3 at all.

They've pushed 8c Tiger Lake so far out that it is beginning to overlap with the potential launch dates for Alder Lake-S.

Sounds like what's happening with Ice Lake SP. In before Sapphire Rapids SP and Alder Lake S are accordingly delayed as well. *shrugs* Seriously, what was the last new product Intel made available on time?

 

[jpiniero]

A fab can't easily add leading edge capacity quickly. They would need customer orders or at least projections a year+ in advance to adjust future capacity.

Right but Intel would have had to agree to this a long time ago. And it would not be a small order either.

 

[mikk]

Sounds like what's happening with Ice Lake SP. In before Sapphire Rapids SP and Alder Lake S are accordingly delayed as well. *shrugs* Seriously, what was the last new product Intel made available on time?

What is your source for the ADL-S delay?

And I don't think high frequencies is that much process related necessarily.

Apparently it is. 10nm+ -->10nm SuperFin +1 Ghz

 

[moinmoin]

What is your source for the ADL-S delay?

None. Just that Intel is the one having to prove being able to deliver on time.

Apparently it is. 10nm+ -->10nm SuperFin +1 Ghz

With Intel's tight coupling of process and silicon design one can't tell either way. We don't even know the yield, only that Intel so far has been incapable of launching dies beyond a specific die size and number of cores, thus keeping them all in the mobile market.

 

[Mopetar]

Even fewer than now?! Hardly seems worth it for intel from that aspect. AMD only released three SKUs and had to raise their prices by $50.

The reason for the constraints is that the initial run of consoles have eaten up a lot of their wafers. One estimate from a report was something like 75-80% of their 7nm wafers went to the SoCs for Sony and Microsoft to have enough consoles for the launch window. Add in a GPU release with one of the larger dies AMD has done in a while and it isn't hard to see why they do t have more products rolling out the door right now.

That won't last forever of course, but I think the demand will outstrip supply for a while longer. The $50 could be in response to that, but I think it's mainly because AMD has the better product now and can charge more for it so they still would have increased prices even if the supply were better.

Intel seem to generally out-clock AMD so I think they design for high frequencies effectively.

Some of it is the process being so refined at this point that lets them keep pushing it farther and farther. At one of their presentations where they were talking about 10nm (it may have been one from a few years ago so things may have changed as that's been refined behind closed doors for the most part) they had a slide that showed the next 10nm desktop part having a lower clock than the current 14nm+++ (or whatever number of pluses it had) and pointed out that because the 14nm was so refined it would out-clock the newer chip.

You can design for higher clocks, but Intel learned the folly of chasing that above all else and the clock speeds haven't increased all that much in a way they might with a targeted design. Look at RDNA2 vs. the original. Same process but the clock speeds increased considerably instead of just adding an extra 100 MHz to the top end of the most expensive part.

 

[Bam360]

Are we sure AMD is not using N7P? I mean, they are saying it's 7nm, but honestly it is weird seeing all products getting significant frequency improvements, not only Zen3 and RDNA2, but also Cezanne features much higer clocks in the integrated Vega iGPU, same architecture but almost 15% higher clocks (1750 vs 2000MHz). You are not getting that boost within the same node and same architecture unless you increase significantly the power consumption, and in Laptop APU it would be really weird doing that. The frequency increase in general of Zen3 and Vega would be in line of a node refinement, while RDNA2 would probably be the combination of the two, node refinement and higher clocking architecture.