Relevancy of RISC-V ISA?

[moinmoin]

What is RISC-V?

"RISC-V (pronounced "risk-five") is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles. In contrast to most ISAs, the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software."
https://en.wikipedia.org/wiki/RISC-V

The aim is to offer several CPU designs under a BSD license.

RISC-V Foundation: https://riscv.org/


Why ask the relevancy question now of all times?

"The European Processor Initiative (EPI), an ambitious program to develop a pair of chips for domestic supercomputers, is poised to change the way Europe does HPC. And although the work is still very much in its early stages, it looks like the Europeans have selected their preferred processor architectures: Arm and RISC-V."
https://www.top500.org/news/european-program-to-develop-supercomputing-chips-begins-to-take-shape/

And in a move that commonly backfires, Arm apparently and surprisingly felt obliged to create a website specifically assembling 'facts' that speak against using RISC-V.
https://riscv-basics.com/
Are they only preparing or already feeling the heat?
Edit: By July 11th Arm took the site off again, it can still be viewed at https://web.archive.org/web/20180708231736/https://riscv-basics.com/

 

[Thala]

Currently the RISC-V specification is very barebone - hardly any security concepts, no SIMD extensions and virtualization and user-mode extensions are in draft. So the market for RISC-V is currently very restricted to micro-controller like implementations. Also there is the inherent danger of fragmentation - as no party is obligated to strictly follow specs and likely doing custom extensions.
As was mentioned in the article linked above:

https://www.top500.org/news/european-program-to-develop-supercomputing-chips-begins-to-take-shape/

The ARMs form the basis as high performance application cores while the RISC-V are supporting as the micro-controllers for acceleration engines - most likely employing custom extensions as well.

 

[whm1974]

There is actually several RISC-V boards you purchase from SiFive:
www.sifive.com

 

[Thala]

There is actually several RISC-V boards you purchase from SiFive:
www.sifive.com

The SiFive U54 core is "the worlds fastest" RISC-V core - but it is slower than Cortex A35 at roughly the same area - and quite a bit slower than Cortex A53 and A55. Yet you can order the development board from SiFive for like $999 - compared to the 30-40$ Cortex A53 development boards, which typically also include a GPU, you can buy literally everywhere.

RISC-V is ok, when you want to hack together a controller core quickly with likes of Synopsis processor designer - but thats about it - at least currently. In addition licensing a RISC-V core from SiFive might be a good alternative for likes of Cadence Xtensa LX or Synopsis ARC HS cores for industrial and embedded use-cases. I also assume that license fees are well below of what ARM is asking for. Essentially that is where i see their niche.
Still a threat for ARMs R and M line of cores.

 

[Qwertilot]

As long as Arm don't get too greedy they'll be fine. If they do then....

 

[whm1974]

The SiFive U54 core is "the worlds fastest" RISC-V core - but it is slower than Cortex A35 at roughly the same area - and quite a bit slower than Cortex A53 and A55. Yet you can order the development board from SiFive for like $999 - compared to the 30-40$ Cortex A53 development boards, which typically also include a GPU, you can buy literally everywhere.

RISC-V is ok, when you want to hack together a controller core quickly with likes of Synopsis processor designer - but thats about it - at least currently. In addition licensing a RISC-V core from SiFive might be a good alternative for likes of Cadence Xtensa LX or Synopsis ARC HS cores for industrial and embedded use-cases. I also assume that license fees are well below of what ARM is asking for. Essentially that is where i see their niche.
Still a threat for ARMs R and M line of cores.

Keep in mind RISC-V is just starting out. The ISA is scalable from micro-controllers to PCs and Supercomputers.

 

[Thala]

Keep in mind RISC-V is just starting out. The ISA is scalable from micro-controllers to PCs and Supercomputers.

What precise ISA features are you referring to which are specific to micro-controller, PCs and supercomputers - and part of the RISC-V ISA specification?

 

[whm1974]

What precise ISA features are you referring to which are specific to micro-controller, PCs and supercomputers - and part of the RISC-V ISA specification?

It is a general purpose ISA. I've been sort of keeping track of it since I heard about it. There are also the lowRISC guys as well.
https://www.lowrisc.org/

 

[Thala]

It is a general purpose ISA. I've been sort of keeping track of it since I heard about it. There are also the lowRISC guys as well.
https://www.lowrisc.org/

Ok since you are dodging my question and now bring in another term "general purpose ISA". What precisely makes this ISA different compared to say ARMv8 ISA? I just see very ordinary stuff in there and quite a few gaps.

 

[whm1974]

Ok since you are dodging my question and now bring in another term "general purpose ISA". What precisely makes this ISA different compared to say ARMv8 ISA? I just see very ordinary stuff in there and quite a few gaps.

Well I'm petty far from being an expert on ISAs and CPUs. I just know what I know from reading the FAQs and watching some of the videos the RISC-V Foundation guys put out.

 

[Thala]

Just look at the 2018 workshop of what needs to be done:

2018 initiatives

• Working to prepare the base ISA for ratifications
• Formal spec in progress
• Hypervisor spec done, need implementations
• Crypto in progress
• J (dynamic translation / runtimes) in progress
• Packed SIMD in progress
• Security task group ongoing
• Fast interrupts started
• Trace started

There are just big holes everywhere in the ISA and architecture specification - holes that you neither find in current ARMv8 nor x86/x64. So it is currently pretty much work-in-progress. And even if they have closed the all the gaps some times in the future, there is nothing particularly special on conceptional level about the ISA - aside from the fact that it is free.
As i said above, using RISC-V today is fine as long as we are talking micro-controllers - for something more complex there is way to go.

 

[whm1974]

The fact the ISA is open and free is the whole point of RISC-V. Yes it started out as a research project over at Berkeley that is getting a lot of attention for many people and companies.

I'm not saying that this is the greatest thing since sliced bread, but it is promising.

 

[Nothingness]

The fact the ISA is open and free is the whole point of RISC-V.

The fact the ISA is open might create a horrible mess and a fragmentation that could make developer life a hell. I've been enduring that with MIPS some years ago where, for instance, the R5900 (the one found in the Sony PS2) had obsolete unsupported toolchains.

 

[teejee]

The fact the ISA is open might create a horrible mess and a fragmentation that could make developer life a hell. I've been enduring that with MIPS some years ago where, for instance, the R5900 (the one found in the Sony PS2) had obsolete unsupported toolchains.

The ISA is very clearly specified with certain optional parts. All normal RISC-V CPU cores will of course adhere to the specifications. It would be very strange to add/skip certain parts "just because".
There will of course be specific products where you add instructions that are core parts of that product, like a purpose specific accelerator/microcontroller.
These instructions will then be handled outside of the toolchain, for example with a lib coded in assembler that handles the performance critical parts.
This is not fragmentation in a negative sense.

RISC-V open up a completely new field of innovation in the world of CPU/microcontroller/SOC. So I'm very positive to RISC-V
But products based on RISC-V is by no means ready to compete with current solutions in smartphones, PC and servers. That is probably 5+ years in the future.

 

[Nothingness]

The ISA is very clearly specified with certain optional parts. All normal RISC-V CPU cores will of course adhere to the specifications. It would be very strange to add/skip certain parts "just because".
There will of course be specific products where you add instructions that are core parts of that product, like a purpose specific accelerator/microcontroller.
These instructions will then be handled outside of the toolchain, for example with a lib coded in assembler that handles the performance critical parts.
This is not fragmentation in a negative sense.

I'm afraid I wasn't precise enough in my comment: I'm specifically talking about the possibility to add new instructions, not about the core instruction set. What will happen when a CPU maker decides to have his own SIMD extension? He's the right to implement it and still being called RISC-V; he will then have to develop his own toolchain which will likely rot. This is exactly what happened to the MIPS chip designed by Toshiba and Sony. And one can also consider what it cost to developers to have to support both AMD and Intel extensions to x86.

For your ISA and its extensions you want it to be defined by a single centralizing entity, and forbid all other extensions; or allow them but then the offending chip should not pretend to be a RISC-V chip.

I'm talking from an industry point of view. As a research vehicle I find RISC-V great

 

[teejee]

I'm afraid I wasn't precise enough in my comment: I'm specifically talking about the possibility to add new instructions, not about the core instruction set. What will happen when a CPU maker decides to have his own SIMD extension? He's the right to implement it and still being called RISC-V; he will then have to develop his own toolchain which will likely rot. This is exactly what happened to the MIPS chip designed by Toshiba and Sony. And one can also consider what it cost to developers to have to support both AMD and Intel extensions to x86.

For your ISA and its extensions you want it to be defined by a single centralizing entity, and forbid all other extensions; or allow them but then the offending chip should not pretend to be a RISC-V chip.

I'm talking from an industry point of view. As a research vehicle I find RISC-V great

But I do talk about adding instructions, please check my post again.
RISC-V vector ISA is more or less complete, so no company will develop a similar general vector extension now because that product would be very difficult to sell.
And concerning a more specialized vector extension, please see my earlier post. In short: the extension is the key selling point for that product, and using an assembler lib is not a bigger hassle than struggle with drivers ( normal case today is to use IP outside of the CPU core for acceleration).

 

[sdifox]

Has it reached OpenSPARC T2 level yet?

 

[Nothingness]

But I do talk about adding instructions, please check my post again.
RISC-V vector ISA is more or less complete, so no company will develop a similar general vector extension now because that product would be very difficult to sell.
And concerning a more specialized vector extension, please see my earlier post. In short: the extension is the key selling point for that product, and using an assembler lib is not a bigger hassle than struggle with drivers ( normal case today is to use IP outside of the CPU core for acceleration).

Have you ever endured the pain of obsolete un-maintained toolchain and libraries for a CPU with proprietary ISA extensions? Because I can guarantee you that this is what will happen to any exotic ISA extension that will be developed for RISC-V. Wish you the best

 

[teejee]

Has it reached OpenSPARC T2 level yet?

It is an ISA, not a product. But I'm certain it is as capable as SPARC v9 used in OpenSPARC T2.

 

[Nothingness]

Has it reached OpenSPARC T2 level yet?

Since you are talking about an implementation: RISC-V still is in its infancy and has only been demonstrated on low perf chips, so it's quite far from T2 at the moment. See this: https://www.sifive.com/

 

[sdifox]

Since you are talking about an implementation: RISC-V still is in its infancy and has only been demonstrated on low perf chips, so it's quite far from T2 at the moment. See this: https://www.sifive.com/

my point being OpenSPARC T2 is available now, it is open source, it is decade old, why start from scratch?

 

[teejee]

Have you ever endured the pain of obsolete un-maintained toolchain and libraries for a CPU with proprietary ISA extensions? Because I can guarantee you that this is what will happen to any exotic ISA extension that will be developed for RISC-V. Wish you the best

Well, I'm certain we'll see successful RISC-V products (including products with custom extensions).

I honestly doesn't see the issue here. You only use custom extensions if they give a big advantage, and then it is worth extra effort to maintain. If a core with custom extension doesn't give big advantages, then of course use 100% pure RISV-V instead.

 

[teejee]

my point being OpenSPARC T2 is available now, it is open source, it is decade old, why start from scratch?

Because SPARC is a dead ISA standard. And OpenSPARC T2 is a pretty standard server chip, this not were RISC-V will take off.

And RISC-V is excellent for new and innovative processors since it allows for custom instructions.

Think IoT, embedded, toys, education, research, accelerators etc and not server, pc and smartphone when it comes to RISC-V

 

[whm1974]

Because SPARC is a dead ISA standard. And OpenSPARC T2 is a pretty standard server chip, this not were RISC-V will take off.

And RISC-V is excellent for new and innovative processors since it allows for custom instructions.

Think IoT, embedded, toys, education, research, accelerators etc and not server, pc and smartphone when it comes to RISC-V

While the biggest market at first is likely to be in education and research and maybe hobbyist, the RISC-V ISA is intended to replace all other ISAs for everything.

 

[Nothingness]

While the biggest market at first is likely to be in education and research and maybe hobbyist, the RISC-V ISA is intended to replace all other ISAs for everything.

Like all ISA. What makes it different from other ISA? Can you list the features that make it stand out from the crowd?

And no, extensions are not enough to sustain that claim; many previous ISA allowed that (including ARM twenty years ago, and MIPS, and ARC, etc.). So what exactly makes you believe RISC-V marketing?