Perhaps it would be necessary first to define some "standard workload."
There can't be one. If you examine the voltage tolerances of the 7nm process as implemented in Matisse, you will begin to see why the boost behavior is so wonky. The amount of voltage you can "safely" feed the chip is entirely related to current draw and temperature. You can feed up to 1.47v handling background threads, while hitting TDC/EDC limits restricts you to about 1.325v or so. Actual FIT tables vary from chip to chip.
Anyway, your typical Matisse requires somewhere around 1.45-1.47v to hit 4.6 GHz reliably, assuming it can even go that high (e.g. it's a 3900x). So you can't really expect that speed under normal boost behavior when any more than one core is engaged, because engaging more cores by necessity increases current draw, causing the dynamic boost map to draw voltage limits down according to the FIT tables. You CAN manipulate this process somewhat by fiddling with voltage (and therefore, temperature) in ways that are invisible to the boost algorithms - by manipulating LLC settings or by applying voltage offsets. In general, default boost behavior likes LOWER voltage than expected, while PBO likes HIGHER. In general. You can also manipulate voltage in such a way as to improve MT boost behavior (default) while hurting ST boost behavior.
The other thing to consider is that temperature has an enormous effect on the voltage required to achieve stability on Matisse. Der8auer documented this effect shortly after launch. The boost algorithm can safely try out higher clocks without (necessarily) pumping more voltage if it stays cool during operation. That's one of the reasons to use negative voltage offsets and/or to encourage vdroop with low LLC settings. The boost algorithm is a bit volt-happy, so if you can get it to run cooler by just undervolting the thing without the algorithm knowing it's going on, it'll see lower-than-expected temps and attempt higher clocks. If it works you get more performance and if it doesn't you get clock stretching (ugh).
Anyway, going back to temperature . . . boost behavior is governed by hotspot temperatures, not temperatures measured at the edge of the die. Temp monitoring programs won't show this since AMD chose to report only the hottest temps on the CCDs to you (HWiNFO64 can report per-CCD temps, if you want them). That's a
good thing since it prevents wingnuts from overriding or otherwise ignoring hotspot temp limits risking damage to their CPUs. Radeon VII taught those of us who bought it to respect the hotspot temps above all else. Tdie is meaningless in this brave new sub-10nm world. Those hotspots are small, and it's really hard to cool them. I want you to consider that my watercooling solution is complete overkill and can probably handle ~1kW heat load with a coolant temperature delta of 5C. And that's a conservative estimate. A 3900x in default behavior mode can't sustain more than 142W through the socket under any circumstance - it'll power throttle. If I were cooling nothing but a hot plate with uniform heat flux across its entire surface and a total heat flux of 142W, the block would probably keep it within 10C of ambient, if not lower. Instead, if I run Prime95 SmallFFTs which pushes that chip to 90% of 142W (127W - I think my voltage adjustments are messing with the boost algorithm's ability to max out the chip) and I let it run for a wee bit, it'll hit temps of 58C with an ambient temp of ~28C according to the motherboard case temp sensor. It appears as though adding more cooling capacity wouldn't help. The loop is now limited by my inability to get heat away from the specific hotspots on the chiplets quickly enough for the loop to do anything with it. The chiplets have to reach temps like 58C before they stop heating up. Oh, and even worse: according to HWiNFO64, nearly half of the 3900x's power consumption isn't even represented by the chiplets themselves. The rest of it is the I/O die. During this activity of Prime95 SmallFFTs @ ~3.9 GHz on all cores, CPU core current averages ~61a and CPU core power averages ~70W. So in actuality, a heat load of 70W generates temps of 58C with a massive ambient cooling solution. Holy crapoly. We are going to need something a lot better than indium solder and copper heatspreaders to get that chiplet heat spread out and into our cooling solutions. If we had that, cooling the chiplets would be trivial, and we could achieve reliably higher clockspeeds at voltages of 1.325v-1.36v which in turn would yield higher boost clocks in MT scenarios. It would also make overclocking a lot more fun.