Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[soresu]

Medusa Point is like 6 different parts.
Which one?

The one Strix Point's top end SKU will be replaced by.

 

[adroc_thurston]

The one Strix Point's top end SKU will be replaced by.

That's gfx13.
Kind of, Medusa1-hi also slots into the same niche in places and that one is 8CU gfx11.5.

 

[reaperrr3]

The one Strix Point's top end SKU will be replaced by.

Where iGFX power isn't that important and only needs to be "good enough":
N3P/C SoC die (4+4+2 cores, 8 RDNA 3.5 CUs)
+ 12C N2P CCD

( = Medusa1-hi)


Where iGFX power is needed:
like above, but RDNA3.5 CUs disabled and AT4 attached as chiplet.

( = Medusa Premium)

 

[adroc_thurston]

Where iGFX power is needed:
like above, but RDNA3.5 CUs disabled and AT4 attached as chiplet.

oh no.
not how any of that works.

 

[soresu]

Another GFX125x µArch device reported in drivers from Phoronix:

AMD "GFX1251" Target Added To LLVM As Latest RDNA 4.5 APU - Phoronix

www.phoronix.com

They seem pretty sure it's APU related 🤔

 

[adroc_thurston]

Another GFX125x µArch device reported in drivers from Phoronix:

AMD "GFX1251" Target Added To LLVM As Latest RDNA 4.5 APU - Phoronix

www.phoronix.com

They seem pretty sure it's APU related 🤔

Its MI400.

 

[soresu]

Its MI400.

That was also my assumption.

Presumably like with MI350 it has at least 2 different dies corresponding to GFX1250 and 1251.

One for HPC and one for AI/ML.

 

[adroc_thurston]

Presumably like with MI350 it has at least 2 different dies corresponding to GFX1250 and 1251.

MI350 doesn't have a discrete ML config though.
That's why gfx950 is a single part.

 

[Kepler_L2]

Another GFX125x µArch device reported in drivers from Phoronix:

AMD "GFX1251" Target Added To LLVM As Latest RDNA 4.5 APU - Phoronix

www.phoronix.com

They seem pretty sure it's APU related 🤔

That's MI430X (HPC stick)

 

[soresu]

That's MI430X (HPC stick)

I figured as much.

 

[basix]

Another GFX125x µArch device reported in drivers from Phoronix:

AMD "GFX1251" Target Added To LLVM As Latest RDNA 4.5 APU - Phoronix

www.phoronix.com

They seem pretty sure it's APU related 🤔

That's MI430X (HPC stick)

From the Phoronix news:

The documentation patch confirms GFX1251 is an APU part just like GFX1250.

Does that mean, that all MI400 variants are APUs and therefore feature integrated Zen 6 CPUs / CCDs?

If yes:
Wouldn't it be ideal, to put the CCDs on the MID chiplets? Then you do not waste area on the main AIDs and bandwidth requirements of the CPU cores are not too huge (MID to AID chiplet interface does not limit in any way).
I think of something like shown in the sketch I have drawn below.

 

[adroc_thurston]

Does that mean, that all MI400 variants are APUs and therefore feature integrated Zen 6 CPUs / CCDs?

None of them are, they just have xGMI host attach.

 

[basix]

Hmm, interesting. So you have basically "remote CCDs" from the Zen 6 host CPU and you can let the system act like it is a "native APU" (from a programmer's point of view)?

How well does that work considering latencies etc.? You get at least one additional hop and then there is the physical distance between MI400 and the host CPU.
But from an integration etc. point of view that concept is kinda neat. And probably the same what Nvidia is doing since Grace-Hopper.

 

[adroc_thurston]

So you have basically "remote CCDs" from the Zen 6 host CPU and you can let the system act like it is a "native APU" (from a programmer's point of view)?

same as MI250X nodes.

How well does that work considering latencies etc.? You get at least one additional hop and then there is the physical distance between MI400 and the host CPU.

It's a GPU. And DMA is DMA.