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Discussion RDNA4 + CDNA3 Architectures Thread

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DisEnchantment

Golden Member
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With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits
Or Phoronix

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it :grimacing:

This is nuts, MI100/200/300 cadence is impressive.

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Previous thread on CDNA2 and RDNA3 here

 
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Is this accurate they got rid of GDS and GWS ? So last terascale GCN remnants from rdna4 ?
Wouldnt this mean higher software overhead more complex scheduler. Guess the added new GL1 would mitigate shared memory and Inter-wavefront Communication.
(I have 38C fever so i may be talking bs)
 
if (info->gfx_level >= GFX10 && info->gfx_level < GFX12) fprintf(f, " l1_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024));

If i understand right 1mb L1 cache size?
 
if (info->gfx_level >= GFX10 && info->gfx_level < GFX12) fprintf(f, " l1_cache_size = %i KB\n", DIV_ROUND_UP(info->l1_cache_size, 1024));

If i understand right 1mb L1 cache size?
That piece of code just outputs L1 cache size if the arch is GFX10 or 11. It's converting bytes into KB by dividing it by 1024 and will display l1_cache_size = some KB. Looks like data log into a file stream.
 
Strange, TPU specs show 256 in RDNA3

NV helping sell Radeon?
Idk im super sick but i guess the new gl cache that is between 1 and 2 is either 128 or 256. So they got rid of 64 GDS and the new cache is taking its place ?
 
doesn't really matter for any modern shader workload
But will it break New Vegas? Only one way to find out!
Wouldnt this mean higher software overhead more complex scheduler
No it just means some things have to join the dodo.
CDNA axed these a whole ago.
So they got rid of 64 GDS and the new cache is taking its place ?
No, GDS is gone. All the _global stuff went to GMEM thru L2 forever anyway.
 
What are peoples estimates on the Blender RT score using zluda for RDNA4?

I think it will be better than 7900 XTX
I more interested in future improvement of HIP RT (or perhaps more cross platform Intel alternatives sh.

Zluda is at best only going to translate the non HW RT accelerated backend, which is only going to see less and less development as time goes on vs the main Optix backend.
 
Don't be so confident. I think AMD had originally intended this as a small launch.
They do have some extra time to prepare given the delay.
Valve adds RDNA 4 support to Steam OS

People are taking this as Valve doing a SteamConsole regen. But isn't this just support for future SteamOS Desktop release?
Good. They will take advantage of Nvidia paper launch period.

Honestly, Navi 44 should have been ready too. AMD would basically offer top to bottom SKUs while Nvidia supply is small.
 
Nobody has posted this yet, anywhere.
Now I'm starting to remember some interesting research from years ago.
If elements of this shared L1 paradigm are in RDNA4 that would be very cool indeed.
 
That test device had a discrete mobile GPU equivalent to a cut down strix halo. I guess it depends on if valve gets the better deal on 6600s or the cut down strix halo

Lilac is just a test motherboard from AMD, as mentioned above. Some confusion appeared when Fremont appeared with a Lilac board because some there are some geekbench results with a 6600S GPU, but others without.




That was using Lilac board, which is the Rembrandt socket. Valve was likely testing how the Lenovo Legion Go S performed with Proton.
Valve's logs show them getting development input from Quantum Computer which is the Steam Deck's manufacturer. Is Quantum Computer making the Legion Go S?

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There's also mention of implementing HDMI CEC in Fremont, which the Legion Go S doesn't have.

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