Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[SolidQ]

They have probably not made any new rdna3 for a while now.

except 7650GRE, need get rid bad wafers before N44

 

[Tuna-Fish]

Let me rephrase that, they are probably still making RDNA3 cards. The economics for AIB manufacture are much more favorable for slow continuous production. But the chips they are putting in those cards were all made a long time ago, and they are probably not making any more.

 

[marees]

Let me rephrase that, they are probably still making RDNA3 cards. The economics for AIB manufacture are much more favorable for slow continuous production. But the chips they are putting in those cards were all made a long time ago, and they are probably not making any more.

You mean the chips were baked in the oven, a long time ago.
But these cold chips are being packed into fresh GPU cards

Why not bake less RDNA 3 ?
Or did they place RDNA 3 orders for the chips when RDNA 2 was at its peak due to covid shortage

 

[Tuna-Fish]

You mean the chips were baked in the oven, a long time ago.
But these cold chips are being packed into fresh GPU cards

Yep.

Why not bake less RDNA 3 ?
Or did they place RDNA 3 orders for the chips when RDNA 2 was at its peak due to covid shortage

Yep. It's all based on estimation of demand. They overestimated, so they have too much of them. They may have underestimated some other product, and now have too little of it. The fundamental problem here is that the timeline from ordering chips from TSMC to delivery of actual product to consumers is way too long for product cycles. You cannot really respond to demand, you just estimate it and hope you got it right. If you guessed too high, you get stuck with piles of rapidly depreciating chips that cost you a pretty penny, if you guessed too low you run out of product to sell. Both situations suck, but the former sucks more. They are not really trading off between products, as the relevant process has slack at TSMC.

 

[Mahboi]

but different instances?

https://twitter.com/x/status/1844356879771959775

Wait I just realised, that means that on CES they'll advertise both Halo and RDNA 4?
Sounds like mixed signals already.

"this is our new top tier amazing APU with our new-old RDNA 3.5 that has meh raytracing that's still amazing raytracing, and this is our real new architecture that has actual raytracing hardware that makes even more amazing raytracing"

 

[jpiniero]

"this is our new top tier amazing APU with our new-old RDNA 3.5 that has meh raytracing that's still amazing raytracing, and this is our real new architecture that has actual raytracing hardware that makes even more amazing raytracing"

I imagine Lisa will spend the entire time on Strix Halo talking about AI.

 

[SolidQ]

RDNA4 is 8x2? Based on Kepler_l2 info

 

[soresu]

"this is our new top tier amazing APU with our new-old RDNA 3.5 that has meh raytracing that's still amazing raytracing, and this is our real new architecture that has actual raytracing hardware that makes even more amazing raytracing"

They'll probably just downplay Halo's RT to focus on overall perf.

 

[Mahboi]

I imagine Lisa will spend the entire time on Strix Halo talking about AI.

They'll probably just downplay Halo's RT to focus on overall perf.

Likely that yep.
Just talk about the 64 Go, mucho AI, remember how AI you can AI, faster than AI can AI, HAIlo is just the most AI, AI.
AI AI AI AI AI AI

 

[itsmydamnation]

View attachment 109134
So, half NVLink 4's throughput? Thats not half bad for a first gen.

400gbps vs 800 gbps ethernet is the same key/encode/optics just more lanes. Not much point doing more until 3.dj which increase data rate per lane.

 

[Mahboi]

400gbps vs 800 gbps ethernet is the same key/encode/optics just more lanes. Not much point doing more until 3.dj which increase data rate per lane.

3.dj?

 

[itsmydamnation]

3.dj?

802.3dj

 

[Mahboi]

802.3dj

Makes more sense, I was thinking of Daft Punk or something for a second there...

 

[Mahboi]

Networking is kind of a sore spot for me so I'm really hoping for someone clever to do a good Pensando P4/NVLink competitor review. Real curious to see how it compares.

 

[itsmydamnation]

Makes more sense, I was thinking of Daft Punk or something for a second there...

i dont know NVlink well , but wiki has 25gbps per lane for NVlink5.0 , so im assuming based off SFP28 targeted standards , so not even using PAM4. this would mean that at the MAC level NV is a technology generation behind. Not that it really matters, because ultimately what will drive scale is overall network fabric architecture vs number of PCI lanes attached/allocated.

DPU are a bit of a wank , really all they are doing is moving switch fabric logic to the NIC , this way the edge intelligence can be a physical hop closer to the CPU/GPU. Modern high end Carrier protocols ( Segment Routing ) push alot of capabilities for multipathing , traffic engineering , affinity / anti-affinity to the edge device. So i expect all of forest's comments to be in effect , lets pick up the current carrier MPLS stack ( IS-IS / BGP , SR , PCE ,PCC ) and extend the boundary one hop. Nothing that he talked about is new from a high end high performance carrier network perspective.

But i can see how it would help AI workloads that are push 95% fabric bandwidth , normally in networking your ringing major alarms for upgrades at => 70%

 

[Saylick]

RDNA4 is 8x2? Based on Kepler_l2 info

There’s 2 Ray Accelerators in a RDNA2/3/3.5 WGP and each RA can do 4 box tests per clock or 1 triangle tests per clock.

RDNA4 either doubles the number of RAs or each RA can do 2x the throughput. Not sure of which it will be but RDNA4 should be twice as performant at minimum.

 

[marees]

Navi 44 seems much bigger than polaris 14 / navi 24.

Seems more comparable to navi 23 🤔

https://twitter.com/x/status/1845710789950484950

Package sizes:

Navi 23: 35 x 35mm
Navi 44: 29 x 29 mm

 

[Kepler_L2]

Navi 44 seems much bigger than polaris 14 / navi 24.

Seems more comparable to navi 23 🤔

https://twitter.com/x/status/1845710789950484950

Package size is influenced not just by die size but also I/O capabilities. N44 is very N23-like in this regard with 128-bit bus and (I think) 8x PCIe.

 

[ToTTenTranz]

Package size is influenced not just by die size but also I/O capabilities. N44 is very N23-like in this regard with 128-bit bus and (I think) 8x PCIe.

Is RDNA4 PCIe 4 or 5?

8GB VRAM + 8x PCIe 4.0 doesn't bode well for a GPU that is supposedly replacing Navi 22 in raster performance.

 

[Kepler_L2]

Is RDNA4 PCIe 4 or 5?

8GB VRAM + 8x PCIe 4.0 doesn't bode well for a GPU that is supposedly replacing Navi 22 in raster performance.

N48 is Gen5 x16. N44 I assume is Gen5 x8.

 

[SolidQ]

What was comparable to 4090, N42 or N41?

 

[static shock]

What was comparable to 4090, N42 or N41?

Was the N41 the halo radeon. Now N48 is the strongest Radeon and is not here to outperform Nvidia halo now.

 

[marees]

Was the N41 the halo radeon. Now N48 is the strongest Radeon and is not here to outperform Nvidia halo now.

My understanding:

N44 = 5060 / 4060 ti
N43/N48 = 5070 / 4070 super / 4070 ti
N42 = 5080 / 4080 super
N41 = 4090

Was there a N40c on top of N41 ??

 

[static shock]

Wow. 399 is possible of there's not much power consumption to package it. Developing the cards costs much more, 3NE is not cheap but hey if they can get this performance at 2.5 times less power consumption is a solid win for AMD. $399 for such a strong card is a winner.

 

[static shock]

My understanding:

N44 = 5060 / 4060 ti
N43/N48 = 5070 / 4070 super / 4070 ti
N42 = 5080 / 4080 super
N41 = 4090

Was there a N40c on top of N41 ??

Its more about HD 5870/5850(7800 xt sucessor) being N48 and 5770/5750 being N44(RX 7600 sucessor). No GTX 570/580 competitor. Got it?


Disclaimer: i'm not a tech journalist and have no NDA to hide anything, these rumor posts are just Guesses of what can happen. They did Zen1 they did Zen5 they did 4850 why they can't do another marvel like these?