Nope, nothing stops you from building a chungus if you have class-leading PPA.
That was quite literally the issue with small die strategy: they won majorly on PPA and capitalized exactly zero times on it.
And then NV went back to PPAmaxing with Kepler and there you go.
Of course I don't know if they might've lied, but I remember an article (might've even been here on anandtech) according to which DAAMIT's big R700 would also have been only 800 ALUs, for RV770 they only stripped down other things to reduce die size (possibly including ROPs though, which *did* matter for perf/clk at that time).
But yeah, it's been maddening how AMD never did the right thing with the right IP.
- RV670 with a 5th SIMD: Would've been way more competitive vs. G94.
- A big R700 with 2 SE, 2x6 SIMDs (960 ALUs) and 32 ROPs would've still been sub-400mm² and demolished GT200.
- RV870 with 24 SIMDs @ 900 MHz would've still been below 400mm², relatively cool and efficient, and enough to beat the GTX 480 in anything but tesselation.
The 58x0 were also priced
too aggressively, AMD was far too afraid of Fermi being good and self-deterred themselves into making no money with that gen, even though they could have.
- Tahiti with 4 SE, 40 CUs and 64 ROPs (close to Hawaii specs) would've been ~450mm², but would've demolished GK104 and given GK110 a hard time.
- Pitcairn with 24 CUs would've given anything below the GTX 680 a hard time.
- Hawaii with just 4 CUs more and some GCN3 tech (DCC, doubled L2) could've kept the mem interface power consumption at saner levels and would've had an easier time competing at least against GM204.
- Tonga was the worst PPA part of all GCN gens, so much wrong with that design, a waste of space and opportunity in so many regards
- A big Polaris with 52-56 CUs, 64 ROPs and 384bit MI could've beaten the 1070 at least, and would've been only like 360mm², much smaller than Vega10 and not much bigger than GP104, so margins wouldn't have been much worse than Nvidia's.
- Navi10 with 48 CUs would've done a lot better against Turing, allowing higher prices.
- Navi22 with 48 CUs would've been only like 7% bigger, for at least ~12-15% higher perf, enough to do better against the 3070(Ti), allowing higher prices.
The sheer length of this list speaks volumes.
It's like some managers at AMD were so obsessed with GPU PPA they forgot that higher performance allows for higher prices, and that sometimes just a few more SIMDs/CUs make for better $PA.
Meanwhile, AMD kept wasting lots of area and margin on APU IGPs that were completely bandwidth-starved and would've barely lost performance by removing 25-40% of the SIMDs/CUs from Llano all the way to Picasso, before sanity returned. Mindboggling stuff.
As much as I want AMD to become fully competitive in dGPU again (and no, not to buy NV cards cheaper, but rather because I'd buy a good AMD card competitive in PPW in a heartbeat):
As 3060 Ti owner, who was able to play MW5 Clans at an image quality rivaling the good ol' 4xSGSSAA DX9 days only thanks to DLSS, I unfortunately have to strongly disagree.
I could care less about RT, but when implemented well, DLSS is a game changer AMD currently has no proper answer to, at least in terms of image quality.
And I'm frankly skeptical about how much FSR4 will improve things.
AMD surely won't spend big money to build server farms just to train their FSR4 algos, so I have a hard time imagining they can catch up and are at risk to fall behind further, actually.
Nvidia has reached a critical mass of financial advantage that allows them to literally buy themselves feature advantages that even a perfect
hardware gen of AMD would only help so much against, which is worrying but in part AMD's own fault for botching too many opportunities in the past.