Discussion RDNA 5 / UDNA (CDNA Next) speculation

[Tuna-Fish]

seems typo from AMD. it's Verona

It's not a legit slide deck from AMD until you find embarrassing typos.

 

[soresu]

seems typo from AMD. it's Verona

Ah fair Verona!

 

[del42sa]

https://wccftech.com/next-gen-hbm-a...gb-capacity-per-24-hi-stack-embedded-cooling/

Looking at the details for HBM4, the memory aims to offer a data rate of 8 Gbps with a 2048-bit IO, 2.0 TB/s of memory bandwidth per stack, 24 Gb capacity per die for up to 36-48 GB memory capacity, and a per-stack power package of 75W. HBM4 goes with the standard direct-to-chip (D2C) Liquid cooling and employs a custom HBM-based die (HBM-LPDDR).

Interestingly, AMD's Instinct MI400, which launches next year too, takes things up a notch versus Rubin and is aiming to offer 432 GB of HBM4 capacity with memory bandwidth of up to 19.6 TB/s.

 

[soresu]

https://wccftech.com/next-gen-hbm-a...gb-capacity-per-24-hi-stack-embedded-cooling/

Looking at the details for HBM4, the memory aims to offer a data rate of 8 Gbps with a 2048-bit IO, 2.0 TB/s of memory bandwidth per stack, 24 Gb capacity per die for up to 36-48 GB memory capacity, and a per-stack power package of 75W. HBM4 goes with the standard direct-to-chip (D2C) Liquid cooling and employs a custom HBM-based die (HBM-LPDDR).

Interestingly, AMD's Instinct MI400, which launches next year too, takes things up a notch versus Rubin and is aiming to offer 432 GB of HBM4 capacity with memory bandwidth of up to 19.6 TB/s.


View attachment 125570

Embedded cooling, aka DARPA ICEcool.