There was nothing wrong with rdram. Actually it's very well engineered for minimum latency and maximum bandwith efficiency. There ain't any unnecessarily latency involved, only that 1 or 2 ns related to little bit longer address and data path chain but that is only way to make such a high speed busses. DDR3 has exactly same address bus chaining type as drdram and have similarly longer latency for last chip of chain.
Actually drdram was well ahead latency wise all sdram variants, every memory chip has 32 independent pages to keep open so with eg 16 memory chips sdram has possibility keep 8 pages open versus 256 pages drdram. With open page hit memory latency is much lower than miss. At 90's there was no memory controller made which could really support what drdram was cabable of, for example intel I850 was cabable of keeping 8 pages open.....
And there was so much more engineered to rdram which was absent from Jedec-memories, for example memory controller and memory chips load capasitance was adaptive so you could mix and match different manufacturers memory modules without problems, something that really good memory standard need but what newer wasn't jedec priorities, threw away you old memory for compatibility sake instead......