RAM question

[Solodays]

WHat's all these number means 2-2-2-5, 2-2-2-3, 1-3-5-4 etc

 

[cantbprince]

Those are ram timings

 

[GreatBarracuda]

BASICS - RAM TIMINGS/LATENCIES - WHAT THE HELL ARE THOSE??

 

[suicidalpigeon]

the lower the better.

 

[Solodays]

so timing is the most cruial part of the rams?

 

[designit]

Originally posted by: Solodays
WHat's all these number means 2-2-2-5, 2-2-2-3, 1-3-5-4 etc

"1T/2T memory timing; Use this option to set you memory timing
Cas#latency(Tcl): this feature controls the latency between the memory read command and the time it becomes available. lower better but too low may cause memory loss of data and cause error
Ras# to Cas#(Trcd): The Bios feature allows you to set the delay between Ras and Cas signals. the appropriate delay for your memory module is reflected in its rated timning. In JEDEC spec. it is the 2nd number in the three or four number sequence. because this delay occurs whenever the row is refreshed or a new row is activated, reducing the delay improves performance. Therefore, it is recommended that you reduce the delay to 3 or 2 for better memory performance. but if you use a value too low for this your memory will become unstable. If your system become unstable after using too low # for Ras to Cas , you should increase it or reset it to spec. Interestingly, by increasing this Ras to Cas if you ran into a snag during overclocking, will increase the memory clock speed. so playing with this number is very crucial for hitting you overclocking just right. start lowering until it is unstabel, and then go up untill stabel. It is like tuning your carburetor in your old car. if anyone has tuned a carburrator screws.
Min Ras# active time (Tras): Like Dram Act to PreChrg CMD, the Bios feature controls the memory bank's minimum row active time (tRAS). This constitudes the time when a row is activated until the time the same row can be deactivated(pulsation of a row). If the tRAS period is too long, it can reduce performance by unnecessary delay of the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated quicker-less time used.
However if the tRAS period is too short, there may not be enough time for burst transfer to next row. This will reduce performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency+tRCD+2 clock cycle. For example, if you set CAS latency to 2 clock cycle and tRCD to 3 clck cycle, the optimum tRAS value would be 7 clock cycles=2-3-7
But if you start getting memory errors or system crash, increase tRAS value one(1) clock cycle at time untile system stable.
Row precharge Time (Trp): You can set the time to precharge. "

if confused? dont be it will take time and trial /error to be a good OC man/woman.

 

[hurtstotalktoyou]

Originally posted by: Solodays
so timing is the most cruial part of the rams?

Not at all. Bus speed is the most important part. For example, 400 MHz memory with 3-4-4-8 timings is still faster than 333 MHz memory with 2-2-2-5 timings. But, within a particular bus speed, lower timings will improve performance.