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RAM modules with SRAM row cache

Is it? I looked on several DRAM manufacturer's sites and couldn't find any info. I may just have no been looking hard enough.


*EDIT*

Found it. It seems to be patented by a company called Ramtron. But there is still the question: why hasn't it been used?
 
Interesting concept. Thoughts on why it hasn't been done:

1) Manufacturing difficulties? Beyond the slight die size increase, you're significantly adding to the complexity of the circuits you have to put into the RAM chip. It may be difficult to physically integrate SRAM into the middle of the memory arrays like that.

2) Licensing difficulties? If the company that holds the patent wants an exorbitant amount of money to let someone build these, that could affect things. If they prove it would work, though, someone would eventually license this for big servers/mainframes, etc.

3) Not enough benefit? The article mentions increased bandwidth, but that's not *all* that important for most applications. If there are other penalties involved (such as writing through the cache being slower, or initial row reads having a longer latency when doing sequential operations, or increased die complexity reducing max clock rates), that could be a reason not to do it.

4) Obsoleted? That review was over three years old, and at that point basically *nobody* expected DDR to do the things it's done (go up to and beyond 250Mhz base clock rate). This technology may just not be needed right now.
 
(1) It's patented.
(2) These tricks tend to be difficult and expensive to implement (SRAM isn't cheap!), while at the same time getting run over by progress in DRAM technology in general. In SDRAM times, a similar thing called Virtual Channel SDRAM was pursued, among others by VIA who actually made supporting chipsets. Actual DIMMs have turned up, few in number, minimal in performance advantage, much more expensive than plain SDRAM DIMMs.
 
Yeah, I went on to read about a bunch more similar idead, and they ended up dying just as you described. One question though; What exactly is DDR3? I've been looking around and I can't find a clear definiton compared with DDR or DDR II. I know that DDRII is really quad-pumped not 'double data rate' as the name implies, but I can't find any specific info on DDR3. The only thing that I keep finding is that DDR3 uses on-die termination, but I had thought that was also part of DDRII. Any information would be appreciated as always.
 
There is very little information about DDR-III available at present, mainly because the specification has not been finalised. Once the specification is finalised, and the manufacturers start producing samples, then you'll have all the information you need. This probably won't be until next year.

It seems likely that DDR-III will allow faster DDR buses, in the same way as DDR-II, from the outside, is still 'double-data-rate' just faster than DDR - so, the interface should be essentially the same, apart from the essential changes such as voltages, timings, termination, etc. DDR-II memory uses 4 SDRAM channels internally, which run at half the external bus speed; a buffer is used to convert this wide, slow internal bus to the faster, narrower external bus. I presume that in DDR-III there will be 8 internal SDRAM channels which run at 1/4 the external bus speed.
 
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