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I vaguely recall there being some limitation, or at least speed differential, when using Double Banked DIMMs on some Dual Channel SocketA boards. Can someone clarify that issue and whether it exists for A64?
Also in some cases the Command rate is automatically reduced to 2T which makes it much slower (Not as bad on A64 but KILLS the P4 and AXP) because instead of transmitting data on the rise and the fall of the clock it transmits only on the IIRC rise.
it was on the INQ. only for new stepping AMD CPUS. dunno if the new stepping has been implemented yet. definately by mid year when the intro dual core cpus.
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