Our Computer Architecture prof (who hasn't seemed very current on the latest hardware) says two things about the P4 that, to my knowledge, aren't true:
1) The P4 has "direct access" to system memory, without going through the chipset/FSB. Essentially, there is a physical connection between the CPU and the RAM that can bypass the North Bridge (or whatever hub Intel calls it.)
2) The P4's L2 cache is partly "external" and partly "on die."
As for #1, to my knowledge, no current architecture enables direct CPU / RAM access without first going through the memory controller on the motherboard chipset. The upcomming Hammer from AMD is the first chip to feature an integrated memory controller.
And for #2, I'm certain that all 256k of the P4's L2 cache is on die.
Am I right here?
Modus
1) The P4 has "direct access" to system memory, without going through the chipset/FSB. Essentially, there is a physical connection between the CPU and the RAM that can bypass the North Bridge (or whatever hub Intel calls it.)
2) The P4's L2 cache is partly "external" and partly "on die."
As for #1, to my knowledge, no current architecture enables direct CPU / RAM access without first going through the memory controller on the motherboard chipset. The upcomming Hammer from AMD is the first chip to feature an integrated memory controller.
And for #2, I'm certain that all 256k of the P4's L2 cache is on die.
Am I right here?
Modus