Questions about P4 Architecture

[Modus]

Our Computer Architecture prof (who hasn't seemed very current on the latest hardware) says two things about the P4 that, to my knowledge, aren't true:

1) The P4 has "direct access" to system memory, without going through the chipset/FSB. Essentially, there is a physical connection between the CPU and the RAM that can bypass the North Bridge (or whatever hub Intel calls it.)

2) The P4's L2 cache is partly "external" and partly "on die."

As for #1, to my knowledge, no current architecture enables direct CPU / RAM access without first going through the memory controller on the motherboard chipset. The upcomming Hammer from AMD is the first chip to feature an integrated memory controller.

And for #2, I'm certain that all 256k of the P4's L2 cache is on die.

Am I right here?

Modus

 

[JameSF]

I think you're right on both points. All memory transactions have to go through the FSB/North Bridge. There are embedded uP's that have integrated memory controllers that have a direct link to memory.

 

[Locutus4657]

All of the P4's cache is on die, 256K in Willamet, 512 in Northwood.

The P4 does not have an integrated memory controller, but AMD's Hammer will :-D



<< Our Computer Architecture prof (who hasn't seemed very current on the latest hardware) says two things about the P4 that, to my knowledge, aren't true:

1) The P4 has "direct access" to system memory, without going through the chipset/FSB. Essentially, there is a physical connection between the CPU and the RAM that can bypass the North Bridge (or whatever hub Intel calls it.)

2) The P4's L2 cache is partly "external" and partly "on die."

As for #1, to my knowledge, no current architecture enables direct CPU / RAM access without first going through the memory controller on the motherboard chipset. The upcomming Hammer from AMD is the first chip to feature an integrated memory controller.

And for #2, I'm certain that all 256k of the P4's L2 cache is on die.

Am I right here?

Modus >>

 

[majewski9]

you are right on both points!!

 

[pm]

Could your professor be talking about the IBM Power4 (P4) rather than the Intel Pentium 4 (P4)? Both points are correct, I believe, if we are referring to the Power4 instead of the Pentium 4 - and it's not too much of a stretch to call both the "P4".

 

[Elledan]

<< Could your professor be talking about the IBM Power4 (P4) rather than the Intel Pentium 4 (P4)? Both points are correct, I believe, if we are referring to the Power4 instead of the Pentium 4 - and it's not too much of a stretch to call both the "P4". >>


There is, however, a noticable difference in performance between these two CPUs 😉

 

[Modus]

Nope, he was definitely talking about the Pentium 4. Intel's Netburst Architecture, to be precise.

I was gonna put up my hand in lecture but I didn't want to risk geekish humiliation until I was 100% sure. I don't think he'll argue with an Intel engineer and a bunch of hardened AT forum jockeys.

Thanks guys.

Modus

 

[imgod2u]

Where the hell is this and what class. It's kinda disturbing that college professors are this misinformed.

 

[CTho9305]

i'd pay $250 for a P4 (1.6ghz+ preferred) processor from your prof... if its the right P4 😉

 

[aka1nas]

I don't expect too much from my college professors in comp sci.😉 One of my professors had no clue what I was talking about when I told him that a drive in my RAID 0 array died and I no longer had my programming project to turn in.

 

[ShadowWolf]

LOL -- sounds almost like DeVRY...

 

[Evadman]

Can I borrow your credit card?

Lol, you can even add it to your shoping cart 🙂

 

[davesaudio]

BOY, sure wish uProcessors existed when I went to School....
(oh crap-have I jast admitted how old I am?...)



<< Our Computer Architecture prof (who hasn't seemed very current on >>



Oh I guess that's not true , there were some big -mother prototype boards we had to program via a hex keypad -ultimately less powerful than a PIC.

sometimes you can end up writing a lot of code to emulate a transistor and couple of passives(grin)