- Aug 19, 2007
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AMD finally seems to have a good cache structure all around with Zen, something they have not had in quite some time. Bulldozer was a mess all over, whereas Phenom had good L1 and L2 caches, but L3 was never overly great.
So my question is, what was with the Phenom II's 48-way L3 cache, and BD's 64 (!) way L3? I've never seen anywhere near that many sets before or since. Did that contribute to their horrid latency? Was there some reasoning behind doing this?
Unrelated but fun trivia since I was reading the CPU upgrade history thread, regarding Duron. Duron had more L1 cache than L2 cache. Talk about odd!
EDIT, I just looked up the first K10 with the 2MB cache, it was 32-way. That seems closer to normal, except it seems like a lot of ways for such a small cache.
So my question is, what was with the Phenom II's 48-way L3 cache, and BD's 64 (!) way L3? I've never seen anywhere near that many sets before or since. Did that contribute to their horrid latency? Was there some reasoning behind doing this?
Unrelated but fun trivia since I was reading the CPU upgrade history thread, regarding Duron. Duron had more L1 cache than L2 cache. Talk about odd!
EDIT, I just looked up the first K10 with the 2MB cache, it was 32-way. That seems closer to normal, except it seems like a lot of ways for such a small cache.
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