adroc_thurston
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DrMrLordX
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Damn he went that far? Does @adroc_thurston even post there? Things are getting too hot around here. Folks need to chillax a little bit.
moinmoin
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He always had been of the outspoken kind in forums. It's just sad this is no longer backed with any excellent public analysis like he did in AT articles.
I remind people that one of the reasons Andrei left this forum (not AT) was constant unfounded criticisms by some here. OTOH I guess he could not tell us much anyway due to where he works now.
That’s the one on a different die, i.e. cheaper physically speaking. The others are just Elites binned down. So tbh it’ll be fine and suggests they’re going to take it mainstream if it’s like that and with an 8c max.
poke01
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llvm-project/llvm/lib/Target/AArch64/AArch64SchedOryon.td at 8aebe46d7fdd15f02a9716718f53b03056ef0d19 · llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - llvm/llvm-project
github.com
Decoder width : 14-wide
Reorder buffer : 376 entries
Unless I missed something it's the dispatch width which is 14 uops. It's not the same as a 14 wide instruction decoder.
llvm-project/llvm/lib/Target/AArch64/AArch64SchedOryon.td at 8aebe46d7fdd15f02a9716718f53b03056ef0d19 · llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - llvm/llvm-project
Decoder width : 14-wide
Reorder buffer : 376 entries
Where did you see this originally?llvm-project/llvm/lib/Target/AArch64/AArch64SchedOryon.td at 8aebe46d7fdd15f02a9716718f53b03056ef0d19 · llvm/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - llvm/llvm-project
Decoder width : 14-wide
Reorder buffer : 376 entries
poke01
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DisEnchantment
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Dispatch width is extremely wide. Since there is no uop cache those uops should come fully from instruction decode. Compared to 6 vs Z4 or 8 for Z5. But not apples to apples comparable
Same mis-predict penalty vs Z4
Same L1 latency vs Z4
It has lower latency for vector (neon), but not apples to apples comparable vs x86 vector
ROB is surprisingly conservative for a 2024 core.
Similar amounts of LS and ALU ports compared to Z5, although Z5/Z4 has two additional FP ports. Store and Load queues depths comparable to Z4.
Not sure how branch address are calculated, for instance Z5 has 4 AGUs for those
It looks OK, nothing in particular stands out. If it is mostly an efficiency play then we will see soon.
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That can be quite complex: uops are stored in queues between decoder and dispatch; also a decoder could emit two uops per cycle. For instance a mem operation with writeback can be split in two uops, one going into ALU queue(s) for the writeback of the base register, while the other goes into load/store queue(s). So I'm afraid at this point nothing can be guessed about decoder width (though I agree it's surely wide, but it's unlikely to be 14-wide).
I've often been wrong, so I won't exclude I'm wrong again
I agree with you on all these points. Can't wait to see the reverse engineering of the uarch details by talented hackers! And benchmarks.
PS - A writeback operation in AArch64 is for instance a ldr x0, [x1], #8 which will do the load then add 8 (size of x0) to x1.
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SarahKerrigan
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That can be quite complex: uops are stored in queues between decoder and dispatch; also a decoder could emit two uops per cycle. For instance a mem operation with writeback can be split in two uops, one going into ALU queue(s) for the writeback of the base register, while the other goes into load/store queue(s). So I'm afraid at this point nothing can be guessed about decoder width (though I agree it's surely wide, but it's unlikely to be 14-wide).
I've often been wrong, so I won't exclude I'm wrong again
I agree with you on all these points. Can't wait to see the reverse engineering of the uarch details by talented hackers! And benchmarks.
PS - A writeback operation in AArch64 is for instance a ldr x0, [x1], #8 which will do the load then add 8 (size of x0) to x1.
There's also fusion to consider. As you know, "width" is kind of a fuzzy concept, especially with aggressively OoO machines where number of uops executing in a given cycle can greatly exceed the machine's sustained whole-pipe width.
Note that Neoverse V2, which is emphatically an 8-wide core, is listed as 16-wide in its LLVM machine model. Vendors tend to do the high-level machine-model variables in their own unique ways, often based on quantitative analysis on codegen rather than on the uarch manual.
Went back to that ARM rumor site and found something odd under Cortex X6:
Implication seems to be a new core IP segment between X and A7xx starting with this 'Alto'.
Not sure if this is just a bad translation or not.
Implication seems to be a new core IP segment between X and A7xx starting with this 'Alto'.
Not sure if this is just a bad translation or not.
If ELP = the A5x isn’t that in between A5x and A7x? Or is ELP extra large perf not extra low power?
adroc_thurston
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ELP is the internal terminology for the Cortex X cores.
The X cores previous to Blackhawk were labeled Makalu-ELP and Hunter-ELP internally.
Watch it be barely any different lmao
The battery life is the only real reveal.
Just a guess, it’s gonna be good.
adroc_thurston
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For people with too much money on their hands, there's a board with a Cortex-X3 based Qualcomm SoC:
www.thundercomm.com
The TurboX SOM specification: https://thundercomm.s3.ap-northeast...0-en]_TurboX_C8550_SOM_Product_Brief_V1.0.pdf
$1600 with only 12 GB is way too much for my toying needs
C8550 Development Kit - Thundercomm
Thundercomm TurboX C8550 Development Kit is a high performance Development Kit which is powered by next Gen Flagship Qualcomm® Snapdragon™ QCS8550 processor. It supports Android, featuring in advanced AI increases, huge camera and video advancements and evolved graphics capability. It is an...
QCS8550: https://docs.qualcomm.com/bundle/pu..._QCS8550_QCM8550_PROCESSORS_PRODUCT_BRIEF.pdf
$1600 with only 12 GB is way too much for my toying needs
SarahKerrigan
Senior member
- Oct 12, 2014
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For people with too much money on their hands, there's a board with a Cortex-X3 based Qualcomm SoC:
The TurboX SOM specification: https://thundercomm.s3.ap-northeast-1.amazonaws.com/uploads/web/c8550/[tc-P-1110-en]_TurboX_C8550_SOM_Product_Brief_V1.0.pdfC8550 Development Kit - Thundercomm
Thundercomm TurboX C8550 Development Kit is a high performance Development Kit which is powered by next Gen Flagship Qualcomm® Snapdragon™ QCS8550 processor. It supports Android, featuring in advanced AI increases, huge camera and video advancements and evolved graphics capability. It is an...
QCS8550: https://docs.qualcomm.com/bundle/pu..._QCS8550_QCM8550_PROCESSORS_PRODUCT_BRIEF.pdf
$1600 with only 12 GB is way too much for my toying needs
Embeddedified Snapdragon 8g2, looks like. A little steep for me as well, though certainly quick.
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